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Data Sheet, DS2, Feb. 2001
MUNICH32X Multichannel Network Controller for HDLC P E B 2 0 3 2 1 V e r si o n 2 . 2 PEF 20321 Version 2.2 Interface
Datacom
Never
stop
thinking.
Edition 2001-02-14 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2/15/01.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, DS2, Feb. 2001
MUNICH32X Multichannel Network Controller for HDLC P E B 2 0 3 2 1 V e r si o n 2 . 2 PEF 20321 Version 2.2 Interface
Datacom
Never
stop
thinking.
PEB 20321 PEF 20321 Revision History: Previous Version: Page 47, 43 204 225 257 263 348 351 2001-02-14 Data Sheet 1998-08-01 DS1 DS2
Subjects (major changes since last revision) Package P-TQFP-176-1 removed from User's Manual. Added description of bit shift to chapter Serial PCM Core. Programming examples for IOM-2 single rate clock added. Renamed register bit MODE2.TSF to MODE2.TSR. Changed locations of bits IMRX and IMTX in register SSCIM. Register description IOMSTAT reworked. Added timings for LBI Master Demultiplexed Mode Added timing 19, 19A and 24B toTable 50. Changed timing 23, 25, 27, 28, 31, 24, 35A, 36A and 36C with respect to previous version of the data sheet. Clarified timings for usage of LRDY plus some minor reworks.
344ff
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
PEB 20321 PEF 20321
Preface
This document provide complete reference information about the Multichannel Network Interface Controller for HDLC PEB 20321 (MUNICH32X). Organization of this Document This Data Sheet is divided into 16 chapters. It is organized as follows: * Chapter 1, Overview Gives a general description of the product and its family, lists the key features, and presents some typical applications. Furthermore it lists pin locations with associated signals, categorizes signals according to function and describes signals. * Chapter 2, Serial PCM Core This chapter provides a functional description of the serial interface. * Chapter 3, Basic Functional Principles Provides a description of key concepts including DMA, descriptior operation, buffer management and device configuration. * Chapter 4, Detailed Protocol Description Explains supported protocols and available protocol features. * Chapter 5, Microprocessor Bus Interface The PCI bus interface and the generic bus interface is covered in this chapter. * Chapter 6, Local Bus Interface (LBI) This chapter provides a description of the local bus interface and its DMA modes. * Chapter 7, Synchronous Serial Control (SSC) Interface Provides a detailed description of the SSC interface. * Chapter 8, IOM(R)-2 Interface The functions and features of the IOM-2 interface is covered here. * Chapter 9, General Purpose Port Gives a description of the general purpose port. * Chapter 10, Reset and Initialization This chapter provides information about reset and initialization sequence. * Chapter 11, Slave Register Descriptions Provides an overview of the device's registers and a detailed description of each
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register. * Chapter 12, Host Memory Organization This chapter contains information about the external data structures. * Chapter 13, Boundary Scan Unit * Chapter 14, Electrical Characteristics Gives a detailed description of all electrical DC and AC characteristics and provides timing diagrams and values for all interfaces. * Chapter 15, MUNICH32X Bus Utilization Contains information about bus utilization on the PCI bus for different parameters. * Chapter 16, Package Outline
Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (MUNICH32X), device number (PEB 20321 or PEF 20321), device version (Version 2.2), and in the body of your e-mail: document type (Data Sheet), issue date (2001-02-14) and document revision number (DS2).
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Table of Contents 1 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.4 1.5 1.6 2 3 4 4.1 4.2 4.3 4.4 4.5 5 5.1 5.1.1 5.1.2 5.1.3 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Page 18 19 22 23 25 31 33 36 38 40 42 43 46
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . New or Changed from MUNICH32, PEB 20320 . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply, Reserved and Dedicated Pins . . . . . . . . . . . . . . . . . . . . Local Bus Interface (LBI) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LBI DMA Support and General Purpose Pins . . . . . . . . . . . . . . . . . . . . Synchronous Serial Control and General Purpose Pins . . . . . . . . . . . . PCM/IOM(R)-2 Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial PCM Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Basic Functional Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Detailed Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 TMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 TMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 TMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 V.110/X.30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Microprocessor Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Transactions Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Configuration Space - Detailed Register Description . . . . . . . . . . De-multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus Interface (LBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transactions with Non-intelligent Peripherals . . . . . . . . . . . . . . . . . . . Transactions with Intelligent Peripherals . . . . . . . . . . . . . . . . . . . . . . . Software Arbiter/Data Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LBI External Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . LRDY Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring the External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 135 135 135 137 142 145 145 146 146 147 147 150 150 153 154 155 155
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6.2.6 6.2.7 6.2.7.1 6.2.7.2 6.2.7.3 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.5 6.6 7 7.1 7.2 7.2.1 7.2.2 7.3 7.4 7.5 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.2 9 10 10.1 10.2 11 11.1
External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LBI Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master/Slave Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization of the Master/Slave Bus Arbitration . . . . . . . . . . . . . . . Operation of the Master/Slave Bus Arbitration . . . . . . . . . . . . . . . . LBI Data Mode State Machine (DMSM) . . . . . . . . . . . . . . . . . . . . . . . . . DMSM Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer in Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer in DMA Assisted Mode . . . . . . . . . . . . . . . . . . . . . . . . . DMSM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Device Register Read/Write Operation . . . . . . . . . . . . . . . . . Connection to Common Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . LBI DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Control (SSC) Interface . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operational Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Channel (including MX, MR bits) . . . . . . . . . . . . . . . . . . . . . . Command/Indicate Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-Channel Priority Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interrupt Vector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Interrupt Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I Interrupt Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
156 158 158 160 161 163 163 163 165 165 167 168 171 174 174 178 178 180 184 185 187 189 190 191 191 191 191 193 193 197 198 199 199 199
General Purpose Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Slave Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Register Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
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11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 12 12.1 12.1.1 12.1.2 12.2 12.2.1 12.2.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.11.1 12.11.2 12.11.3 13 14 14.1 14.2 14.3 14.4 14.5 14.6 14.6.1 14.6.1.1 14.6.1.2 14.6.1.3 14.6.2 14.6.3
Register Bit Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUNICH32X Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PCM Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LBI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control and Configuration Block (CCB) in Host Memory . . . . . . . . . . . . . Serial PCM Core CCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LBI CCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Action Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PCM Core Action Specification . . . . . . . . . . . . . . . . . . . . . . . . . LBI Action Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PCM Core Interrupt Vector Structure . . . . . . . . . . . . . . . . . . . . . . Interrupt Bit Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Slot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Receive and Transmit Descriptor Addresses ............. Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PCM Core DMA Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Queues Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PCM Core Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LBI DMA Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
214 214 222 235 249 251 258 269 273 273 273 275 276 276 279 280 283 289 291 303 304 311 316 317 317 318 319
Boundary Scan Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Important Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . De-multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
329 329 332 332 333 334 335 335 336 337 338 342 344
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14.6.3.1 14.6.3.2 14.6.4 14.6.5 14.6.6 14.6.7 15 15.1 15.2 15.2.1 15.2.2 15.2.3 15.2.4 15.3 15.4 16
Local Bus Interface Timing in Slave Mode . . . . . . . . . . . . . . . . . . . Local Bus Interface Timing in Master Mode . . . . . . . . . . . . . . . . . . PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUNICH32X Bus Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Cycle Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Descriptor and Data Processing . . . . . . . . . . . . . . . . . . . . . . Transmit Interrupt Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Descriptor and Data Processing . . . . . . . . . . . . . . . . . . . . . . Receive Interrupt Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Utilization Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Utilization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
344 348 352 354 355 356 357 357 359 359 359 360 360 361 362
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
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List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39
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Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MUNICH32X Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Functional Block Overview of MUNICH32X . . . . . . . . . . . . . . . . . . . . . 43 Block Diagram of MUNICH32X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 General System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 T1/DS1 Mode PCM Frame Timing 1.544 MHz . . . . . . . . . . . . . . . . . . 48 T1/DS1 Mode PCM Frame Timing 1.536 MHz . . . . . . . . . . . . . . . . . . 49 CEPT Mode PCM Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.096 Mbit/s PCM Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.192 Mbit/s PCM Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Example: Programmable Channel Allocation for 32 Time Slots . . . . . 53 Example: Programmable Channel Allocation for 24 Time Slots . . . . . 53 Example: Transmit Bit Shift Programming of 0 and -3 . . . . . . . . . . . . . 53 Multiplex Management Receive Direction . . . . . . . . . . . . . . . . . . . . . . 55 Multiplex Management Transmit Direction. . . . . . . . . . . . . . . . . . . . . . 56 Partitioning of TB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Partitioning of RB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Memory Division (Serial PCM Core) for up to four MUNICH32X . . . . . 59 Handling ofFEand HOLDCondition (VariableSize FrameOriented Protocols) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Handling of E, S, X Changes (Fixed Size Frame Oriented Protocols) 64 Handling of FE Condition (Fixed Size Frame Oriented Protocols) . . 66 Handling of HOLD Condition (Fixed Size Frame Oriented Protocols) . 67 Handling of FE and HOLD Condition (Time Slot Oriented Protocol) . 69 Handling of TH Condition (Variable Size Frame Oriented Protocols) . 72 Handling of TH Condition (Fixed Size Frame Oriented Protocols). . . . 74 Handling of TH Condition (Time Slot Oriented Protocol) . . . . . . . . . . . 75 HandlingofTHand HOLDCondition(VariableSizeFrameOriented Protocols) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Handling of TH and HOLD Condition (Fixed Size Frame Oriented Protocols) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Handling of TH and HOLD Condition (Time Slot Oriented Protocol) . 80 FNUM Reduction in HDLC Transmit Mode . . . . . . . . . . . . . . . . . . . . 84 Example of HDLC Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Receiver Interframe Time-Fill States in HDLC . . . . . . . . . . . . . . . . . . . 89 Example of HDLC Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Example of HDLC Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Example of HDLC Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Example of HDLC Reception with CS = 0 . . . . . . . . . . . . . . . . . . . . . . 95 Example of HDLC Reception with CS = 0 . . . . . . . . . . . . . . . . . . . . . . 96 Example of TMB Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Example of TMB Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82
Data Sheet
Example of TMB Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of TMR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of TMR Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of Data Transfer Synchronization in TMA mode . . . . . . . . . Example of TMA Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of TMA Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...................................................... Example of TMA Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of TMA Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of V.110/X.30 Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . Receiver States in V.110/X.30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of V.110/X.30 Receive Mode . . . . . . . . . . . . . . . . . . . . . . . Example of V.110/X.30 Receive Mode . . . . . . . . . . . . . . . . . . . . . . . Loss of Synchronism in V.110/X.30 . . . . . . . . . . . . . . . . . . . . . . . . . . Master Single READ Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Burst WRITE/READ Access . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus Interface Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . LBI Mailbox Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demultiplexed Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LRDY Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Arbitration (Releasing the Bus). . . . . . . . . . . . . . . . . . . External Bus Arbitration (Regaining the Bus) . . . . . . . . . . . . . . . . . . Connection of the Master and Slave Bus Arbitration Signals . . . . . . Bus Arbitration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers and Port Pins Associated with the SSC . . . . . . . . . . . . . . . Synchronous Serial Channel SSC Block Diagram. . . . . . . . . . . . . . . Serial Clock Phase and Polarity Options . . . . . . . . . . . . . . . . . . . . . . SSC Full Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Half Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Error Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 S/T Interfaces realized by one MUNICH32X and two QUAT(R)-S . . IOM(R)-2 Interface with 2.048 Mbit/s Data Rate . . . . . . . . . . . . . . . . . Monitor Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Handshake Timing in General . . . . . . . . . . . . . . . . . . . . . . . Tx Polling Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Queue Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Bus I/O and Alternate LBI/SSC Functions . . . . . . . Serial PCM Core Control and Configuration Block (CCB) . . . . . . . . . LBI Control and Configuration Block (LCCB) . . . . . . . . . . . . . . . . . . . Serial PCM Core Action Specification . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
103 106 109 112 114 116 117 119 120 123 127 132 133 134 143 143 145 148 151 152 153 154 157 158 160 162 174 175 177 178 181 186 189 191 195 196 231 232 238 274 275 278 288
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Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 Figure 99 Figure 100 Figure 101 Figure 102 Figure 103 Figure 104 Figure 105 Figure 106 Figure 107 Figure 108 Figure 109 Figure 110 Figure 111 Figure 112 Figure 113
Channel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Decoding of Peripheral Queue Interrupt Vectors . . . . . . . . . . . . . . . . 320 Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . 322 Power-up and Power-down Scenarios. . . . . . . . . . . . . . . . . . . . . . . . 329 Power-Failure Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 335 PCI Output Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . 335 PCI Input Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . 336 PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 PCI Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Master Single READ Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Master Burst WRITE/READ Access . . . . . . . . . . . . . . . . . . . . . . . . . .342 LBI Slave: Address Timing in Multiplexed Mode . . . . . . . . . . . . . . . . 344 LBI Slave: Address Timing in Non-Multiplexed Mode . . . . . . . . . . . . 344 LBI Slave: Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 LBI Slave: Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 LBI Master: Read Cycle Timing in Demultiplexed Mode . . . . . . . . . . 348 LBI Master: Write Cycle Timing in Demultiplexed Mode . . . . . . . . . . 348 LBI Master: Read Cycle Timing in Multiplexed Mode . . . . . . . . . . . . 349 LBI Master: Write Cycle Timing in Multiplexed Mode. . . . . . . . . . . . . 349 LBI Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 PCM Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 SSC Serial Interface Timing (Master) . . . . . . . . . . . . . . . . . . . . . . . . 356 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Ideal System, E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Typical System, E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Ideal System, T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Typical System, T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Data Sheet
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List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40
Data Sheet
Page
PCI Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Supply, Reserved and Dedicated Pins . . . . . . . . . . . . . . . . . . 31 Local Bus Interface (LBI) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LBI DMA Support/General Purpose Bus Pins . . . . . . . . . . . . . . . . . . . 36 Synchronous Serial Control (SSC) Interface/General Purpose Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PCM/IOM(R)-2 Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Synchronization Pattern for V.110/X.30-Frames . . . . . . . . . . . . . . . . 121 Framing for Networks with 600-bit/s Data Rate . . . . . . . . . . . . . . . . . .128 Framing for Networks with 1200-bit/s Data Rate . . . . . . . . . . . . . . . . .128 Framing for Networks with 2400-bit/s Data Rate . . . . . . . . . . . . . . . . .129 Framing for Networks with 4800-, 9600-, 19200-, 38400-bit/s Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Non-PCI Pins in the De-multiplexed Bus Configuration . . . . . . . . . . . 142 Supported Commands in De-multiplexed Mode . . . . . . . . . . . . . . . . 144 LBI Peripheral Transaction Options . . . . . . . . . . . . . . . . . . . . . . . . . . 145 LBI Bus Arbitration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Port Control of the SSC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Abort Request from Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 List of Commands and Indications. . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Subfunction Status after Hardware Reset . . . . . . . . . . . . . . . . . . . . . 202 Programming after Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . 203 MUNICH32X Slave Register Set (BAR1). . . . . . . . . . . . . . . . . . . . . . 210 MUNICH32X Mailbox Registers (LBI Side) . . . . . . . . . . . . . . . . . . . . 213 MUNICH32X Direct LBI Access (BAR2) . . . . . . . . . . . . . . . . . . . . . . 213 LBI External Configuration for ESCC2. . . . . . . . . . . . . . . . . . . . . . . . 246 LBI External Configuration for HSCX . . . . . . . . . . . . . . . . . . . . . . . . . 247 LBI External Configuration for FALC54 (HDLC mode) . . . . . . . . . . . 247 Sizes of the Control and Configuration Block . . . . . . . . . . . . . . . . . . 273 Sizes of the LBI Control and Configuration Block . . . . . . . . . . . . . . . 275 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Serial PCM Core Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Serial PCM Core Interrupt Queues . . . . . . . . . . . . . . . . . . . . . . . . . . 318 LBI DMA Controller Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . 318 LBI DMA Controller Interrupt Queues . . . . . . . . . . . . . . . . . . . . . . . . 319 Peripheral Queue Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Boundary Scan Sequence in MUNICH32X . . . . . . . . . . . . . . . . . . . . 323 Boundary Scan Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
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Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55
TA = 0 to + 70 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 TA = 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 PCI Input and Output Measurement Conditions . . . . . . . . . . . . . . . . 336 Number of Wait States Inserted by the MUNICH32X as Initiator. . . . 339 Number of Wait States Inserted by the MUNICH32X as Target . . . . 339 PCI Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 PCI Interface Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 341 Additional De-multiplexed Interface Signal Characteristics . . . . . . . . 343 LBI Slave Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 LBI Master Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 PCM Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 JTAG Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 SSC Serial Interface Timing (Master) . . . . . . . . . . . . . . . . . . . . . . . . 356 List of Abbreviations for PCI Bus Cycle Calculations. . . . . . . . . . . . . 359
Data Sheet
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Data Sheet
17
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Overview
1
Overview
The MUNICH32X is an enhanced version of the Multichannel Network Interface Controller for HDLC, MUNICH32 (PEB 20320, refer to the User's Manual 01.2000). Key enhancements include: * a 33 MHz/32-bit PCI bus Master/Slave interface with integrated DMA controllers for higher performance, lower development effort and risk, * symmetrical Rx and Tx buffer descriptor formats for faster switching, * an improved Tx idle channel polling process for significantly reduced bus occupancy, * an integrated Local Bus Interface (LBI) for connection to other peripherals that do not have a PCI bus interface with DMA capability, * an SSC interface and * an IOM(R)-2 interface. The MUNICH32X provides capability for up to 32 full-duplex serial PCM channels. It performs layer 2 HDLC formatting/deformatting or V.110 or X.30 protocols up to a network data rate of 38.4 Kbit/s (V.110) or 64 Kbit/s (HDLC), as well as transparent transmission for the DMI mode 0, 1, and 2. Processed data are passed on to an external memory shared with one or more host processors. The MUNICH32X is compatible with the LAPD ISDN (Integrated Services Digital Network) protocol specified by CCITT, as well as with HDLC, SDLC, LAPB and DMI protocols. It provides any rate adaption for time slot transmission data rate from 64 Kbit/ s down to 8 Kbit/s and the concatenation of any time slots to data channels, supporting the ISDN H0, H11, H12 superchannels. The MUNICH32X may be used in a wide range of telecommunication and networking applications, e.g. * in switches to provide the connection to a PBX, to a host computer, or as a central Dchannel controller for 32 D-channels, * for connection of up to 4 MUNICH32Xs to one PCM highway to achieve a D-channel controller with 128 channels, * in routers and bridges for LAN-WAN internetworking via channelized T1/E1 or multiple S/T interfaces, * for wide area trunk cards in routers and switches (Frame Relay, ISDN PRI, Internet Protocols, etc.), and * for centralized D- or B-channel packet processing in routers, switches (Frame Relay, Q.931 Signaling, X.25, etc.) Note: In the course of the Data Sheet, the expression `DWORD' always refers to 32-bit words in correspondence to the PCI specification.
Data Sheet
18
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Multichannel Network Interface Controller for HDLC MUNICH32X
PEB 20321 PEF 20321
Version 2.2
1.1
Features
32-channel HDLC controller with PCI interface: * Serial PCM core - Up to 32 independent full-duplex channels - Serial PCM traffic at 2.048, 4.096, 1.544, 1.536, 3.088, 6.176 or 8.192-Mbit/s * Dynamic Programmable Channel Allocation - Compatible with T1/DS1 24-channel and CEPT 32channel PCM byte format - Concatenation of any, not necessarily consecutive, time slots to superchannels - independently for receive and transmit direction - Support of H0, H11, H12 ISDN-channels - Subchanneling on each time slot possible * Bit Processor Functions (adjustable for each channel) - HDLC Protocol - Automatic flag detection - Shared opening and closing flag - Detection of interframe-time-fill change, generation of interframe-time-fill `1's or flags - Zero bit insertion - Flag stuffing and flag adjustment for rate adaption - CRC generation and checking (16 or 32 bits) - Transparent CRC option per channel and/or per message - Error detection (abort, long frame, CRC error, 2 categories of short frames, non-octet frame content) - ABORT/IDLE flag generation - V.110/X.30 Protocol
Type PEB 20321 PEF 20321
Data Sheet
Package P-MQFP-160-1 P-MQFP-160-1
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Overview - Automatic synchronization in receive direction, automatic generation of the synchronization pattern in transmit direction - E/S/X bits freely programmable in transmit direction, may be changed during transmission; changes monitored and reported in receive direction - Generation/detection of loss of synchronism - Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s - Transparent Mode A - Slot synchronous transparent transmission/reception without frame structure - Flag generation, flag stuffing, flag extraction, flag generation in the abort case with programmable flag - Synchronized data transfer for fractional T1/PRI channels - Transparent Mode B - Transparent transmission/reception in frames delimited by 00H flags - Shared opening and closing flag - Flag stuffing, flag detection, flag generation in the abort case - Error detection (non octet frame content, short frame, long frame) - Transparent Mode R - Transparent transmission/reception with GSM 08.60 frame structure - Automatic 0000H flag generation/detection - Support of 40, 391/2, 401/2 octet frames - Error detection (non octet frame contents, short frame, long frame) - Protocol Independent - Channel inversion (data, flags, IDLE code) - Format conventions as in CCITT Q.921 2.8 - Data over- and underflow detected Microprocessor Interface - 32-bit PCI bus interface option, 33 MHz - 32-bit De-multiplexed bus interface option, 33 MHz - 68 channel DMA controller (64 for 32 serial channels, 4 for 2 LBI channels) with buffer chaining capability - Master 4-DWORD burst read and write capability - Slave single-DWORD read and write capability - Interrupt-circular buffers with variable sizes - Maskable interrupts for each channel IOM(R)-2 Interface with on-chip C/I and monitor handlers Synchronous Serial Control (SSC) Interface 8-/16-bit Local Bus Interface (LBI)
*
* * *
Data Sheet
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Overview * General - Connection of up to four MUNICH32X supporting a 128-channel basic access D-channel controller - On-chip Rx and Tx data buffers 256 bytes each - HDLC protocol or transparent mode, support of ECMA 102, CCITT I4.63 RA2, V.110, X.30, DMI mode 0, 1, 2 (bit rate adaption), GSM 08.60 TRAU frames - Loopback mode, complete loop as well as single channel loop - JTAG boundary scan test - 0.5 m low-power CMOS technology - 3.3 V and 5 V voltage supply - TTL-compatible inputs/outputs - 160-pin P-MQFP package
Data Sheet
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Overview
1.2
New or Changed from MUNICH32, PEB 20320
* Symmetrical Rx and Tx Buffer Descriptor formats for faster switching * Improved Tx idle channel polling process, which significantly reduces bus occupancy of idle Tx channels * Additional PCM modes supported: 3.088 Mbit/s, 6.176 Mbit/s, 8.192 Mbit/s * 32-bit PCI bus Master/Slave interface (33 MHz) with integrated DMA controllers for higher performance, and lower development effort and risk * Enhanced Interrupt Structure providing: separate serial PCM Rx and Tx Interrupt Queues in host memory, separate DMA related LBI Rx and Tx Interrupt Queues in host memory, dedicated LBI pass-through, SSC, General Purpose bus and IOM(R)-2 Peripheral Interrupt Queue in host memory * Slave read capability of serial PCM core, LBI, SSC and IOM(R)-2 read/write registers * Time Slot Shift capability * Bit Shift Capability programmable from -4 clock edges to +3 clock edges relative to synchronization pulse, programmable to sample Tx data at either clock falling or rising edge, programmable to sample Rx data at either clock falling or rising edge, * Software initiated Action Request via a bit field in the Command register * Tx End-of-Packet transmitted-on-wire interrupt capability per channel * Tx packet size increased to 16 Kbytes * Rx packet size 8 kbyte limit interrupt disable * Rx Enable bit field of the MODE1 register * Rx Interrupt Disable bit field of the MODE1 register * Tx data tristate control line (TXDEN) * Synchronized data transfer in TMA mode for complete transparency when using fractional T1/PRI channels * Integrated Local Bus Interface (LBI), which allows connection to peripherals that do not provide a PCI bus interface * IOM(R)-2 interface with single and double data rate clock * Collision control on S/T interface by QUAT-S (PEB 2084) via data ready control line (DRDY) * Synchronous Serial Control (SSC) interface * 16-bit General Purpose Bus (8 bits are shared with LBI, the other eight bits are shared with SSC; the respective bits can not be used when LBI and/or SSC are enabled) * Internal Descriptor and Table Dump capability for software development purposes * Little/Big Endian data formats selectable via a bit field in Configuration register
Data Sheet
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PEB 20321 PEF 20321
Overview
1.3
Pin Configuration
(top view)
P-MQFP-160-1
LD10 / A26 LD11 / A27 LD12 / A28 LD13 / A29 LD14 / A30 LD15 / A31 V DD3 V SS TDI TMS TCK TDO RXCLK / DCL RSP / FSC RXD / DD DRDY TXDEN TXD / DU TSP TXCLK GP15 / MCLK GP14 / MTSR GP13 / MRST GP12 / N.C.3 V DD3 V SS V SS V DD3 V SS GP11 / MCS0 GP10 / MCS1 GP9 / MCS2 GP8 / MCS3 TEST DEMUX GP7 / DRQTA GP6 / DRQRA GP5 / DRQTB GP4 / DRQRB GP3 / DACKTA
120 110 100 90
81 80
LD9 / A25 LD8 / A24 V DD3 V SS LD7 / A23 LD6 / A22 LD5 / A21 LD4 / A20 LD3 / A19 LD2 / A18 LD1 / A17 LD0 / A16 V SS V DD3 V SS RST CLK GNT REQ AD31 AD30 AD29 AD28 V DD3 V SS AD27 AD26 AD25 AD24 C / BE3 IDSEL AD23 AD22 V DD3 V SS AD21 AD20 AD19 AD18 AD17
121
130 70
140
MUNICH32X PEB 20321
60
150 50
160 1
10
20
30
41 40
GP2 / DACKTB GP1 / DACKRA GP0 / DACKRB LCSI LCSO LALE LINTO LINTI1 LINTI2 LBHE V DD3 V SS LWR LRD LRDY LHLDA LHOLD LBREQ W/R RESERVED 2 LA0 / A0 V DD3 V SS LA1 / A1 LA2 / A2 LA3 / A3 LA4 / A4 LA5 / A5 LA6 / A6 LA7 / A7 LA8 / A8 LA9 / A9 V DD3 V SS LA10 / A10 LA11 / A11 LA12 / A12 LA13 / A13 LA14 / A14 LA15 / A15
AD16 C / BE2 FRAME V DD3 V SS IRDY TRDY DEVSEL STOP RESERVED 1 PERR SERR PAR V DD5 V DD5 V DD3 V SS C / BE1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 V DD3 V SS AD8 C / BE0 AD7 AD6 AD5 AD4 AD3 AD2 V DD3 V SS AD1 AD0 INTA
ITP10338
Figure 1
Pin Configuration
Data Sheet
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PEB 20321 PEF 20321
Overview Signal Type Definition: The following signal type definitions are mainly taken from the PCI Specification Revision 2.1: in out t/s, I/O s/t/s
Input is a standard input-only signal. Totem Pole Output is a standard active driver. Tri-State or I/O is a bi-directional, tri-state input/output pin. Sustained Tri-State is an active low tri-state signal owned and driven
by one and only one agent at a time. (For further information refer to the PCI Specification Revision 2.1)
o/d
Open Drain allows multiple devices to share as a wire-OR. A pull-up
is required to sustain the inactive state until another agent drives it, and must be provided by the central resource.
Data Sheet
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PEB 20321 PEF 20321
Overview
1.3.1
Table 1 Pin No.
PCI Bus Interface Pins
PCI Bus Interface Pins Symbol I/O t/s Function Address/Data Bus A bus transaction consists of an address phase followed by one or more data phases. When MUNICH32X is Master, AD(31:0) are outputs in the address phase of a transaction. During the data phases, AD(31:0) remain outputs for write transactions, and become inputs for read transactions. When MUNICH32X is Slave, AD(31:0) are inputs in the address phase of a transaction. During the data phases, AD(31:0) remain inputs for write transactions, and become outputs for read transactions. AD(31:0) are updated and sampled on the rising edge of CLK. Command/Byte Enable During the address phase of a transaction, C/BE(3:0) define the bus command. During the data phase, C/ BE(3:0) are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE0 applies to byte 0 (lsb) and C/BE3 applies to byte 3 (msb). When MUNICH32X is Master, C/BE(3:0) are outputs. When MUNICH32X is Slave, C/BE(3:0) are inputs. C/BE(3:0) are updated and sampled on the rising edge of CLK.
140, 141, 142, AD(31:0) 143, 146, 147, 148, 149, 152, 153, 156, 157, 158, 159, 160, 1, 19, 20, 21, 22, 23, 24, 25, 28, 30, 31, 32, 33, 34, 35, 38, 39
150, 2, 18, 29
C/BE(3:0)
t/s
Data Sheet
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PEB 20321 PEF 20321
Overview Table 1 Pin No. 13 PCI Bus Interface Pins (cont'd) Symbol PAR I/O t/s Function Parity PAR is even parity across AD(31:0) and C/BE(3:0). PAR is stable and valid one clock after the address phase. PAR has the same timing as AD(31:0) but delayed by one clock. When MUNICH32X is Master, PAR is output during address phase and write data phases. When MUNICH32X is Slave, PAR is output during read data phases. Parity errors detected by the MUNICH32X are indicated on PERR output. PAR is updated and sampled on the rising edge of CLK. Frame FRAME indicates the beginning and end of an access. FRAME is asserted to indicate a bus transaction is beginning. While FRAME is asserted, data transfers continue. When FRAME is deasserted, the transaction is in the final phase. When MUNICH32X is Master, FRAME is an output. When MUNICH32X is Slave, FRAME is an input. FRAME is updated and sampled on the rising edge of CLK.
3
FRAME
s/t/s
Data Sheet
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PEB 20321 PEF 20321
Overview Table 1 Pin No. 6 PCI Bus Interface Pins (cont'd) Symbol IRDY I/O s/t/s Function Initiator Ready IRDY indicates the bus master's ability to complete the current data phase of the transaction. It is used in conjunction with TRDY. A data phase is completed on any clock where both IRDY and TRDY are sampled asserted. During a write, IRDY indicates that valid data is present on AD(31:0). During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted together. When MUNICH32X is Master, IRDY is an output. When MUNICH32X is Slave, IRDY is an input. IRDY is updated and sampled on the rising edge of CLK. Target Ready TRDY indicates a slave's ability to complete the current data phase of the transaction. During a read, TRDY indicates that valid data is present on AD(31:0). During a write, it indicates the target is prepared to accept data. When MUNICH32X is Master, TRDY is an input. When MUNICH32X is Slave, TRDY is an output. TRDY is updated and sampled on the rising edge of CLK.
7
TRDY
s/t/s
Data Sheet
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PEB 20321 PEF 20321
Overview Table 1 Pin No. 9 PCI Bus Interface Pins (cont'd) Symbol STOP I/O s/t/s Function STOP STOP is used by a slave to request the current master to stop the current bus transaction. When MUNICH32X is Master, STOP is an input. When MUNICH32X is Slave, STOP is an output. STOP is updated and sampled on the rising edge of CLK. Initialization Device Select When MUNICH32X is slave in a transaction, if IDSEL is active in the address phase and C/BE(3:0) indicates an I/O read or write, the MUNICH32X assumes a read or write to a configuration register. In response, the MUNICH32X asserts DEVSEL during the subsequent CLK cycle. IDSEL is sampled on the rising edge of CLK. Device Select When activated by a slave, it indicates to the current bus master that the slave has decoded its address as the target of the current transaction. If no bus slave activates DEVSEL within six bus CLK cycles, the master should abort the transaction. When MUNICH32X is master, DEVSEL is input. If DEVSEL is not activated within six clock cycles after an address is output on AD(31:0), the MUNICH32X aborts the transaction and generates an INTA. When MUNICH32X is slave, DEVSEL is output.
151
IDSEL
I
8
DEVSEL
s/t/s
Data Sheet
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PEB 20321 PEF 20321
Overview Table 1 Pin No. 11 PCI Bus Interface Pins (cont'd) Symbol PERR I/O s/t/s Function Parity Error When activated, indicates a parity error over the AD(31:0) and C/BE(3:0) signals (compared to the PAR input). It has a delay of two CLK cycles with respect to AD and C/BE(3:0) (i.e., it is valid for the cycle immediately following the corresponding PAR cycle). PERR is asserted relative to the rising edge of CLK. System Error The MUNICH32X asserts this signal to indicate a fatal system error. SERR is activated on the rising edge of CLK. Request Used by the MUNICH32X to request control of the PCI. REQ is activated on the rising edge of CLK. Grant This signal is asserted by the arbiter to grant control of the PCI to the MUNICH32X in response to a bus request via REQ. After GNT is asserted, the MUNICH32X will begin a bus transaction only after the current bus Master has deasserted the FRAME signal. GNT is sampled on the rising edge of CLK. Clock Provides timing for all PCI transactions. Most PCI signals are sampled or output relative to the rising edge of CLK. The actual clock frequency is either equal to the frequency of CLK, or CLK frequency divided by 2. The maximum CLK frequency is 33 MHz.
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12
SERR
o/d
139
REQ
t/s
138
GNT
t/s
137
CLK
I
Data Sheet
PEB 20321 PEF 20321
Overview Table 1 Pin No. 136 PCI Bus Interface Pins (cont'd) Symbol RST I/O I Function Reset An asynchronous active low RST signal brings all PCI registers, sequencers and signals into a consistent state. All PCI output signals are driven to their benign state. During RESET all output and I/O pins are in tristate condition with the following exception: TXDEN is active high during RESET. Interrupt Request When an interrupt status is active and unmasked, the MUNICH32X activates this open-drain output. Examples of interrupt sources are transmission/ reception error, completion of transmit or receive packets etc. The MUNICH32X deactivates INTA when the interrupt status is acknowledged via an appropriate action (e.g., specific register write) and no other unmasked interrupt statuses are active. INTA is activated/ deactivated asynchronous to the CLK.
40
INTA
O (oD)
Note: PCI control signals always require pull-up resistors. For the system dependent pull-up recommendation please refer to PCI Specification Revision 2.1 chapter 4.3.3.
Data Sheet
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PEB 20321 PEF 20321
Overview
1.3.2
.
Power Supply, Reserved and Dedicated Pins
Power Supply, Reserved and Dedicated Pins Symbol DEMUX I/O I Function PCI/De-multiplexed Mode Select DEMUX = 0 indicates normal PCI operation. DEMUX = 1 indicates that the MUNICH32X is operated in Demultiplexed mode. Write/Read This signal distinguishes write and read operations in the De-multiplexed mode. It is tristate when the MUNICH32X is in PCI mode. A Pull-Up resistor to VDD3 is recommended if De-multiplexed mode is not used. Reserved A Pull-Up resistor to VDD3 is recommended.
Table 2 Pin No. 86
62
W/R
I/O
10
RES. 1
I/O
61
RES. 2
O
Reserved A Pull-Up resistor to VDD3 is recommended.
5, 17, 27, 37, 47, VSS 58, 69, 92, 94, 95, 113, 124, 133, 135, 145, 155 4, 16, 26, 36, 48, VDD3 59, 70, 93, 96, 114, 123, 134, 144, 154 14, 15 VDD5
-
Ground (0 V) All pins must have the same level.
-
Supply Voltage 3.3 V 0.3 V All pins must have the same level.
-
Supply Voltage 5 V 0.25 V All pins must have the same level.
Data Sheet
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PEB 20321 PEF 20321
Overview Table 2 Pin No. 87 Power Supply, Reserved and Dedicated Pins (cont'd) Symbol TEST I/O I Function Test Input When set to VDD3 the MUNICH32X works in test mode. It must be set to VSS for normal working mode. JTAG Test Clock A Pull-Up resistor to VDD3 is recommended if boundary scan unit is not used. JTAG Test Mode Select A Pull-Up resistor to VDD3 is recommended if boundary scan unit is not used. JTAG Test Data Input A Pull-Up resistor to VDD3 is recommended if boundary scan unit is not used. JTAG Test Data Output
JTAG Test Port for Boundary Scan according to IEEE 1149.1 110 TCK I
111
TMS
I
112
TDI
I
109
TDO
O
Data Sheet
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PEB 20321 PEF 20321
Overview
1.3.3
Table 3 Pin No.
Local Bus Interface (LBI) Pins
Local Bus Interface (LBI) Pins Symbol LA(15:0)/ I/O I/O Function LBI Address These pins provide the 16 bit Address bus for the Local Bus Interface. A Pull-Down resistor to VSS is recommended if LBI is not used. DEMUX Address These pins provide the 16 least significant address lines for the Demultiplexed Interface, when DEMUX = 1. LBI Data These pins provide the 16 bit Data bus for the Local Bus Interface. A Pull-Down resistor to VSS is recommended if LBI is not used. DEMUX Address These pins provide the 16 most significant address lines for the Demultiplexed Interface, when DEMUX = 1. LBI Hold Request LHOLD = 1 is used for normal bus drive mode. LHOLD = 0 requests LBI to enter hold mode. A Pull-Up resistor to VDD3 is recommended if LBI is not used. LBI Bus Request Output LBREQ = 0 to request bus then set LBREQ = 1 after regaining bus. LBI Hold Status As an output, LHLDA = 0 confirms that the LBI bus is in HOLD mode. As an input, LHLDA = 1 means that MUNICH32X must remain in hold mode. A Pull-Up resistor to VDD3 is recommended if LBI is not used. LBI Chip Select Output Used to select LBI external peripheral
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41, 42, 43, 44, 45, 46, 49, 50, 51, 52, 53, 54, 55, 56, 57, 60
A(15:0)
I/O
115, 116, 117, 118, 119, 120, 121, 122, 125, 126, 127, 128, 129, 130, 131, 132
LD (15:0)/
I/O
A(31:16)
I/O
64
LHOLD
I
63
LBREQ
O
65
LHLDA
I/O
76
LCSO
O
Data Sheet
PEB 20321 PEF 20321
Overview Table 3 Pin No. 77 Local Bus Interface (LBI) Pins (cont'd) Symbol LCSI I/O I Function LBI Chip Select Input Used to select MUNICH32X as LBI Slave. A Pull-Up resistor to VDD3 is recommended if LBI is not used. LBI Address Latch Enable A Pull-Down resistor to VSS is recommended if LBI is not used. LBI Read Strobe A Pull-Up resistor to VDD3 is recommended if LBI is not used. LBI Write Strobe A Pull-Up resistor to VDD3 is recommended if LBI is not used. LBI Byte High Enable A Pull-Up resistor to VDD3 is recommended if LBI is not used. LBI Ready Strobe to Extend Cycles A Pull-Up resistor to VDD3 is recommended if LBI is not used. LBI Interrupt Input from Peripheral1 In case of bit HE1 in register LCONF is set (HSCX register decoding selected) this pin must be connected to VDD3 if unused. In case of bit HE1 in register LCONF is reset (ESCC2 register decoding selected) this pin must be connected to VSS if unused.
75
LALE
O
67
LRD
I/O
68
LWR
I/O
71
LBHE
I/O
66
LRDY
I/O
73
LINTI1
I
Data Sheet
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PEB 20321 PEF 20321
Overview Table 3 Pin No. 72 Local Bus Interface (LBI) Pins (cont'd) Symbol LINTI2 I/O I Function LBI Interrupt Input from Peripheral2 In case of bit HE1 in register LCONF is set (HSCX register decoding selected) this pin must be connected to VDD3 if unused. In case of bit HE1 in register LCONF is reset (ESCC2 register decoding selected) this pin must be connected to VSS if unused. LBI Interrupt Output to Local Microcontroller
74
LINTO
O
Data Sheet
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PEB 20321 PEF 20321
Overview
1.3.4
.
LBI DMA Support and General Purpose Pins
LBI DMA Support/General Purpose Bus Pins Symbol DRQTA/ GP7 I/O I I/O I I/O I I/O I I/O O Function DMA Request for Transmit Channel A On reset, pin is General Purpose Bus pin DMA Request for Receive Channel A On reset, pin is General Purpose Bus pin DMA Request for Transmit Channel B On reset, pin is General Purpose Bus pin DMA Request for Receive Channel B On reset, pin is General Purpose Bus pin DMA Acknowledge for Transmit Channel A On reset, pin is General Purpose Bus pin DMA Acknowledge for Transmit Channel B On reset, pin is General Purpose Bus pin
Table 4 Pin No. 85
84
DRQRA/ GP6
83
DRQTB/ GP5
82
DRQRB/ GP4
81
DACKTA/
GP3 80 DACKTB/
I/O O
GP2
I/O
Data Sheet
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PEB 20321 PEF 20321
Overview Table 4 Pin No. 79 LBI DMA Support/General Purpose Bus Pins (cont'd) Symbol DACKRA/ I/O O Function DMA Acknowledge for Receive Channel A On reset, pin is General Purpose Bus pin DMA Acknowledge for Receive Channel B On reset, pin is General Purpose Bus pin
GP1 78 DACKRB/
I/O O
GP0
I/O
Note: If bit `LBI' is set to `1' in register CONF i.e. DMA support for LBI operation is selected controlled by pin numbers 78..85, all unused pins must be connected in accordance with the following recommendation: DRQTA, DRQRA, DRQTB, DRQRB to VSS DACKTA, DACKTB, DACKRA, DACKRB Pull-Up to VDD3 If bit `LBI' is set to `0' in register CONF (RESET value) pins 78..85 provide the General Purpose Port (GPP) pins 0..7. In this case a Pull-Up resistor to VDD3 is recommended for unused pins.
Data Sheet
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PEB 20321 PEF 20321
Overview
1.3.5
Table 5 Pin No. 100
Synchronous Serial Control and General Purpose Pins
Synchronous Serial Control (SSC) Interface/General Purpose Bus Pins Symbol MCLK/ GP15 I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O O I/O O I/O O I/O Function SSC Shift Clock Input/Output On reset, pin is General Purpose Bus pin SSC Master Transmit/Slave Receive On reset, pin is General Purpose Bus pin SSC Master Receive/Slave Transmit On reset, pin is General Purpose Bus pin Reserved when in SSC Mode On reset, pin is General Purpose Bus pin SSC Chip select 0 On reset, pin is General Purpose Bus pin SSC Chip select 1 On reset, pin is General Purpose Bus pin SSC Chip select 2 On reset, pin is General Purpose Bus pin SSC Chip select 3 On reset, pin is General Purpose Bus pin
99
MTSR/ GP14
98
MRST/ GP13
97
N.C.3/ GP12
91
MCS0/ GP11
90
MCS1/ GP10
89
MCS2/ GP9
88
MCS3/ GP8
Data Sheet
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PEB 20321 PEF 20321
Overview Note: Pull-Up resistors to VDD3 are recommended for unused pins independent of whether they are configured as General Purpose Port (GPP) pins 8..15 (RESET value) or as Synchronous Serial Control (SSC) interface via bit `SSC' in register CONF.
Data Sheet
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Overview
1.3.6
Table 6 Pin No. 108
PCM/IOM(R)-2 Interface Pins
PCM/IOM(R)-2 Interface Pins Symbol RXCLK/ I/O I Function Receive Clock Provides the data clock for RXD T1/DS1 24-channel 1.544 MHz 24-channel 1.536 MHz CEPT 32-channel 2.048 MHz 32-channel 4.096 MHz Additional new PCM modes: 3.088 MHz, 6.176 MHz, 8.192 MHz (refer to MODE1 register description) IOM(R)-2 Data Clock Receive Synchronization Pulse This signal provides the reference for the receive PCM frame synchronization. It marks the first bit in the PCM frame. IOM(R)-2 Frame Synchronization Receive Data Serial data is received at this PCM input port. The MUNICH32X supports the T1/ DS1 24-channel PCM format, the CEPT 32-channel PCM format as well as a 32channel PCM format with 4.096-Mbit/s bit rate. IOM(R)-2 Data Downstream Transmit Clock Provides the data clock for TXD (refer to RXCLK). Transmit Synchronization Pulse This signal provides the reference for the transmit frame synchronization. It marks the last bit in the PCM frame. Transmit Data Serial data sent by this PCM output port is push-pull for active bits in the PCM frame and tristate for inactive bits. IOM(R)-2 Data Upstream
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DCL 107 RSP/
I/O I
FSC 106 RXD/
I/O I
DD 101 TXCLK
I I
102
TSP
I
103
TXD/
O
DU
Data Sheet
O
PEB 20321 PEF 20321
Overview Table 6 Pin No. 104 105 PCM/IOM(R)-2 Interface Pins (cont'd) Symbol TXDEN DRDY I/O O I Function Transmit Data Enable Indicates tristate of TXD Data Ready A Pull-Up resistor to VDD3 is recommended if not used.
Note: As a general recommendation 10 K Ohm resistors connected to VDD3 should be used as Pull-Ups and 10 K Ohm resistors connected to VSS should be used as Pull-Downs.
Data Sheet
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PEB 20321 PEF 20321
Overview
1.4
Logic Symbol
Test Interface DEMUX W / R TEST V SS V DD3 V DD5 TCLK TMS TDI TDO 32 AD(31:0) C/ BE(3:0) PAR FRAME IRDY TRDY STOP IDSEL DEVSEL PERR SERR REQ GNT CLK RST INTA 4 RXCLK / DCL RSP / FSC RXD / DD
PCI Interface
MUNICH32X PEB 20321
TXCLK TSP TXD / DU DRDY TXDEN MCS(3:0) MRST MCLK MTSR
PCM / IQM-2 Interface
SSC Interface
16
16
13
LD(15:0) LBI_Ctrl DRQTA DRQRA DRQTB DRQRB DACKTA DACKRA DACKTB DACKRB Local Bus Interface DMA Support Interface
ITL10455
Figure 2
MUNICH32X Logic Symbol
Note: To reduce complexity, the De-multiplexed General Purpose Bus (refer to pin definition table) is not shown here.
Data Sheet
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PEB 20321 PEF 20321
Overview
1.5
Functional Block Diagram
The functional block diagrams are shown in Figure 3 and Figure 4.
PCI / Generic Bus Multiplexed PCI Address / Data Bus 32 32 Optional Generic Address Bus
PCI System Bus Interface with FIFOs DMA Controller 64 Channels Config. and State Memory Serial PCM Core 4 Channels Data FIFOs State Machine LBI MBOX
256 Byte FIFOs
HDLC Controller
LBI Interface PCM Interface IOM -2 Handle
R
SSC Interface
JTAG
8 PCM / IOM -2 Serial Data Interface
R
8 Serial Port
4
8- / 16-Bit
Test Local Interface Bus
ITB10339
Figure 3
Functional Block Overview of MUNICH32X
Data Sheet
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2001-02-14
Figure 4
PCI Interface
Data Sheet
PCI Config Register Register
PCI
PCI Master PCI Arbiter
Register
Register
PCI Slave
16 DWORD RxFIFO Command Gen. 8 DWORD TxFIFO 16 DWORD TxFIFO
Command Gen.
16 DWORD TxFIFO
Interrupt
Command Gen.
16 DWORD RxFIFO
Block Diagram of MUNICH32X
LBI
44
8 DWORD
R
Serial PCM Core
2 *16 DWORD
LBI DMA Controller
256 Byte RB
DMA Controller CM
256 Byte TB
DMSM
Mailbox
HDLC RD
CSR
HDLC TF
LBI Interface
SSC
IOM -2 / Timer
Local Bus Interface
SCC Interface
PCM Serial Interface
ITB10340
PEB 20321 PEF 20321
2001-02-14
Overview
PEB 20321 PEF 20321
Overview The internal functions of the serial PCM core are partitioned into 8 major blocks: 1. PCM Serial Interface - Parallel-Serial conversion, PCM timing, switching of the test loops, controlling of the multiplex procedure. 2. Transmit Formatter TF - HDLC frame, bit stuffing, flag generation, flag stuffing and adjustment, CRC generation, transparent mode transmission and V.110, X.30 80 bit framing. 3. Transmit Buffer TB - Buffer size of 64 DWORDs allocated to the channels, i.e. eight PCM frames can be stored before transmission, individual channel capacity programmable. 4. Receive Deformatter RD - HDLC frame, zero-bit deletion, flag detection, CRC checking, transparent mode reception and V.110, X.30 80 bit framing. 5. Receive Buffer RB - Buffer size of 64 DWORDs allocated to the channels, i.e. eight PCM frames can be stored, individual DWORDs are freely accessible by each channel. 6. Configuration and State RAM CSR - Since the Transmit Formatter, Receive Deformatter are used in a multiplex manner, the state and configuration information of each channel has to be stored. 7. DMA Controller CM/DMAC - Interrupt processing, memory address calculation, chaining list handling, chip configuration. 8. Internal Bus Interface to PCI (IBUS) - On-chip interface, which connects the new functional blocks (LBI, SSC, IOM(R)-2, Global Registers) to the MUNICH32X core; 32-bit de-multiplexed address/data, control signals provided in little-endian format, 33 MHz, synchronous non-burst mode, bus arbitration provided. Note that the structure and functionality of all other MUNICH32X blocks (IOM(R)-2, SSC, LBI) are described in the appropriate sections of this manual.
Data Sheet
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Overview
1.6
System Integration
The MUNICH32X is designed to handle up to 32 data channels of a PCM highway. It transfers the data between the PCM highway and a memory shared with a host processor via a 32-bit PCI bus interface (33 MHz). At the same time it performs protocol formatting and deformatting as well as rate adaption for each channel independently. The host sets the operating mode, bit rate adaption method and time slot allocation of each channel by writing the information into the shared memory. Using subchanneling each time slot can be shared between up to four MUNICH32Xs; so that in one single time slot four different D-channels can be handled by four MUNICH32Xs. Figure 5 gives a general overview of system integration of the MUNICH32X.
CPU
Memory
PCI Bus PCI Arbiter REQ
GNT GNT REQ MUNICH32X GNT REQ MUNICH32X GNT REQ MUNICH32X GNT REQ MUNICH32X
Up to 4 MUNICH32X
PCM Highway (2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 1.536 Mbit/s, 1.544 Mbit/s, 3.088 Mbit/s, 6.176 Mbits)
ITB10341
Figure 5
General System Integration
The PCI bus interface of the MUNICH32X consists of a 32 bit multiplexed data and address bus (AD31 ... AD0), four command/byte enable lines C/BE(3:0), PCI control and bus management lines (PAR, FRAME, IRDY, TRDY, STOP, IDSEL, DEVSEL, PERR, SERR, REQ, GNT), one clock, one reset and one interrupt line. The PCI bus traffic is controlled by the PCI arbiter. It manages the bus request/grant control for up to four independent PCI devices, hence supporting the connection of four MUNICH32X as shown above.
Data Sheet
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PEB 20321 PEF 20321
Serial PCM Core
2
Serial PCM Core
The Serial PCM core provides up to 32 full-duplex channels. The serial PCM interface includes a Rx data (RXD) and a Tx data line (TXD) as well as the accompanying control signals (RXCLK = Receive Clock, RSP = Receive Synchronization Pulse, TXCLK = Transmit Clock, TSP = Transmit Synchronization Pulse). The timings of the receive and transmit PCM highway are independent of each other, i.e. the frame positions and clock phases are not correlated. Data is transmitted and received either at a rate of 2.048 Mbit/s for the CEPT 32-Channel European PCM format (Figure 8) or 1.544 Mbit/s or 1.536 Mbit/s for the T1/DS1 24-Channel American PCM format (Figure 6 and Figure 7). The MUNICH32X may also be connected to a 4.096-Mbit/s PCM system (Figure 9), where it handles either the even- or odd-numbered time slots, so all 64 time slots can be covered by connecting two MUNICH32Xs to the PCM highway. The MUNICH32X also supports three additional PCM highway modes: 3.088 Mbit/s, 6.176 Mbit/s and 8.192 Mbit/s (Figure 10). The actual bit rate of a time slot can be varied from 64 Kbit/s down to 8 Kbit/s for the receive and transmit direction. A fill mask code specified in the time slot assignment determines the bit rate and which bits of a time slot should be ignored. Any of these time slots can be combined to a data channel allowing transmission rates from 8 Kbit/s up to 2.048 Mbit/s. The frame alignment is programmable via register MODE1. Receive and transmit data may be sampled at either rising or falling clock edge, programmable in register MODE2. Note the MUNICH32X may be configured to be fully compatible to the MUNICH32, PEB 20320. The MUNICH32X provides for a programmable bit shift of the transmit and receive synchronization pulse in the range of -4 to 3 bits. Figure 6 to Figure 10 show PCM frame timings with a bit shift of 0 (MODE1.TBS = 4, MODE1.RBS = 4). Figure 13 shows an example for a T1/DS1 transmit PCM frame timing with a bit shift of 0 and with a bit shift of -3. The F-bit for the 1.544 MHz T1/DS1 24-channel PCM format is ignored in receive direction, the corresponding bit is tristate in transmit direction. It is therefore assumed that this channel is handled by a different device. For test purposes four different test loops can be switched. In a complete loop all logical channels are mirrored either from serial data output to input (internal loop) or vice versa (external loop). In a channelwise loop one single logical channel is logically mirrored either from serial data output to input (internal loop) or vice versa (external loop). For a more detailed description of the different loops see Section 12.2.
Data Sheet
47
2001-02-14
PEB 20321 PEF 20321
Serial PCM Core The following drawings show examples for transmit situations in different PCM modes. Note that Figure 6 ... Figure 9 address the case, in which the MUNICH32X is programmed in MUNICH32 mode.
125 s SLOT 0 SLOT 1 F0123456701234567 PCM - Frame SLOT 23 6 TXCLK 7 F 0 1 2 SLOT 0 3 4 5 6 7 SLOT 1 SLOT 23
TSP
TXD
FILL/MASK T1/DS1 - Mode Transmit Frame Timing
~ ~
Fill/Mask : Slot 0 10011000
SLOT 23 6 RXCLK 7 F 0 1 2
SLOT 0 3 4 5 6 7
SLOT 1
RSP
RXD
DATA
DATA
DATA
DATA
DATA
DATA
FILL/MASK T1/DS1 - Mode Receive Frame Timing
Fill/Mask : Slot 0 11010110
ITD10406
Figure 6
T1/DS1 Mode PCM Frame Timing 1.544 MHz
Note 9: A box in a bit of the RXD line means that this bit is ignored. Note 10:The fill/mask bit for the F-bit is not defined. TXD is tristate for the F-bit, and the F-bit is ignored in the receive direction.
Data Sheet 48 2001-02-14
PEB 20321 PEF 20321
Serial PCM Core Note 11:TSP and RSP must have one single rising and falling edge during a 125 s PCM frame.
125 s SLOT 0 SLOT 1 0123456701234567 PCM - Frame SLOT 23 6 TXCLK 7 0 1 2 SLOT 0 3 4 5 6 7 SLOT 1 SLOT 23
TSP
TXD
FILL/MASK T1/DS1 - Mode Transmit Frame Timing
~ ~
Fill/Mask : Slot 0 10011000
SLOT 23 6 RXCLK 7 0 1 2
SLOT 0 3 4 5 6 7
SLOT 1
RSP
RXD
DATA
DATA
DATA
DATA
DATA
DATA
FILL/MASK T1/DS1 - Mode Receive Frame Timing
Fill/Mask : Slot 0 11010110
ITD10407
Figure 7 Note 1: A
T1/DS1 Mode PCM Frame Timing 1.536 MHz box in a bit of the RXD line means that this bit is ignored.
Data Sheet
49
2001-02-14
PEB 20321 PEF 20321
Serial PCM Core Note 2: TSP and RSP must have one single rising and falling edge during a 125 s PCM frame.
125 s SLOT 0 SLOT 1 0123456701234567 PCM - Frame SLOT 31 6 TXCLK 7 0 1 2 SLOT 0 3 4 5 6 7 SLOT 1 SLOT 31
TSP
TXD
FILL/MASK CEPT - Mode Transmit Frame Timing
Fill/Mask : Slot 0 10011000
SLOT 31 6 RXCLK 7 0 1 2
SLOT 0 3 4 5 6 7
SLOT 1
RSP
RXD
DATA
DATA
DATA
DATA
DATA
DATA
DATA
FILL/MASK CEPT - Mode PCM - Frame Timing
Fill/Mask : Slot 0 11010110
ITD10408
Figure 8 Note 1: A
CEPT Mode PCM Frame Timing box in a bit of the RXD line means that this bit is ignored.
Data Sheet
50
2001-02-14
PEB 20321 PEF 20321
Serial PCM Core Note 2: TSP and RSP must have one single rising and falling edge during a 125 s PCM frame.
125 s SLOT 0
01234567
SLOT 1
SLOT 31
TSP
RSP 4.096 Mbit/s PCM-Format: Time-Slot Shift = 0
SLOT 0
~~ ~~
~~ ~~
~ ~
01234567
01234567
SLOT 31
TSP
RSP 4.096 Mbit/s PCM-Format: Time-Slot Shift = 1
~~ ~~
~~ ~~
~ ~
67
01234567
01234567
ITD10409
Figure 9
4.096 Mbit/s PCM Frame Timing
Note: TSP and RSP must have one single rising and falling edge during a 125 s PCM frame.
Data Sheet
51
2001-02-14
PEB 20321 PEF 20321
Serial PCM Core
SLOT 0.a
SLOT 0.b
SLOT 0.c
SLOT 0.d
01234567012345670123456701234567
125 s SLOT 0 a:d
a b c d a
SLOT 1 a:d
b c d a
SLOT 2 a:d
b c d a
SLOT 31 a:d
b c d
TSP
RSP
8.192 Mbit/s PCM-Format: Time-Slot Shift = 0, i.e. Receive/Transmit in Slots 0.a, 1.a, ... 31.a
SLOT 0 a:d
a b c d a
SLOT 1 a:d
b c d a
SLOT 2 a:d
b c d a
~~ ~~
SLOT 31 a:d
b c d
TSP
RSP
8.192 Mbit/s PCM-Format: Time-Slot Shift = 1, i.e. Receive/Transmit in Slots 0.b, 1.b, ... 31.b
~~ ~~
~~ ~~
~ ~
~~ ~~
~ ~
ITD10410
Figure 10
8.192 Mbit/s PCM Frame Timing
Note: TSP and RSP must have one single rising and falling edge during a 125 s PCM frame.
Data Sheet
52
2001-02-14
PEB 20321 PEF 20321
Serial PCM Core
125 s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 x 64 kbit/s 0 1 2 1 3 4 1 5 6 78791
ITD03499
Figure 11
Example: Programmable Channel Allocation for 32 Time Slots
125 s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 x 64 kbit/s
0
1
2
3
4
3
5
1
2
6
ITD03500
Figure 12
Example: Programmable Channel Allocation for 24 Time Slots
TXCLK Bitshift TSP (bitshift of 0) TSP (bitshift of -3) T1/DS1, 1.544 MHz 190 191 190 191 192 F 0 1 2 3 4 3 2 1 0 -1 -2 -3 -4
Figure 13
Example: Transmit Bit Shift Programming of 0 and -3
Data Sheet
53
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles
3
Basic Functional Principles
The MUNICH32X is a Multichannel Network Interface Controller for HDLC, offering a variety of additional features like subchanneling, data channels comprising of one or more time slots, DMI 0, 1, 2 transparent or V.110/X.30 transmission and programmable rate adaption. MUNICH32X performs formatting and deformatting operations in any network configuration, where it implements, together with a microprocessor and a shared memory, the bit oriented part (flag, bit stuffing, CRC check) of the layer 2 (data link protocol level) functions of the OSI reference model. The block diagram is shown in Figure 4. The MUNICH32X is designed to handle up to 32 data channels of a 1.536/1.544 Mbit/s T1/DS1 24-channel, 2.048 Mbit/s CEPT 32channel, 3.088/6.176 Mbit/s 24-channel or a 4.096/8.192 Mbit/s 32-channel PCM highway. The device provides transmission for all bit rates from 8 Kbit/s up to 2.048 Mbit/ s of packed data in HDLC format or of data in a transparent format supporting the DMI mode (0, 1, 2) or V.110/X.30 mode. Tristating of the transmission line as well as switching a channelwise or complete loop are also possible. An on-chip 64-channel DMA generator controls the exchange of data and channel control information between the MUNICH32X and the external memory. The MUNICH32X processes receive and transmit data independently for each time slot and transmission direction respectively (blocks TF = Transmit Formatter, RD = Receive Deformatter). The frame counters are reset by the rising edges of the RSP or TSP line. The processing units TF and RD work with a multiplex management, i.e. only one protocol handler exists, which is used by all channels in a time sharing manner (see Figure 14 and Figure 15). The actual configuration, e.g. transmission mode, channel assignment, fill/mask code or state of the protocol handlers is retrieved from the Configuration and State RAM (CSR) at the beginning of the time slot and reloaded to the CSR at the end. In receive direction, 32 unpacked data bits are first accumulated and then stored into an on-chip receive buffer (RB) for transfer to the shared memory. As soon as the RB receives 32 bits for a channel it requests access to the parallel microprocessor bus. The on-chip transmit buffer (TB) is always kept full of data ready for transmission. The TB will request more data when 32 bits become available in the ITBS (refer to channel specification). These buffers allows a flexible access to the shared memory in order to prevent data underflow (Tx direction) and data overflow (Rx direction). The transmit buffer (TB) has a size of 64 DWORDs (= 256 bytes). In this buffer, data of 8 PCM frames can be stored. In this case, the time between accesses to the shared memory and data supply to the Transmit Formatter is max. 1 ms. In order to meet these requirements, a variable and programmable part of the buffer (ITBS) must be allocated to each data channel (see Figure 16).
Data Sheet
54
2001-02-14
Figure 14
RXD
Bit 1 Bit 2
Bit 0
~ ~ ~ ~
Bit 7
Active Receive X 1 Channel (external)
X2
~ ~ ~ ~
~ ~~ ~
...
Data Sheet
Bit 0 Bit 1 X3 X1 X2
RXCLK
CLK
Active Receive X 0 Channel (internal) Load CD, CSR Data for X 1 into RD RD Protocol Operation disabled RXD Protocol Operation Phase of RD, CM might write new Channel Config Data into CSR Wait Phase no Operation of RD, CM might write new Channel Config Data into CSR
Multiplex Management Receive Direction
55
CD CSR
X1
Reload RD into CSR Protocol Operation disabled
Load CSR Data for X 2 into RD RD Protocol Operation disabled RXD
CSR
RD
CSR CSR
X1
CD CSR
X2
RD CM
FIFO
CM
RD
RD
ITD10411
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
Figure 15
TXCLK
~ ~ ~ ~
~~ ~~ ~~ ~~
~ ~
CLK
~ ~
...
Data Sheet
Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 X0 X1 X1 X2
TXD
Active Transmit Channel (external)
Active Transmit Channel X0 (internal) Load CSR Data for X 1 into TF TF Protocol Operation disabled Protocol Operation Phase of TF, CM might write new Channel Config Data into CSR Wait Phase no Operation of TF CM might write new Channel Config Data into CSR
Multiplex Management Transmit Direction
56
CSR CSR
X1
Reload TF into CSR, CD TF Protocol Operation disabled TXD
TF
CSR CSR
X1
CD
TF CM
FIFO
CM
TF
ITD10412
X1 X2 X0
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles For example: a) 2.048-Mbit/s PCM highway 32 x 64-Kbit/s data channels (8 bits are sent with each PCM frame). Two DWORDs of the buffer are allocated to each data channel. b) 1 x 2.048-Kbit/s data channel The maximum buffer size for one channel (63 DWORDs) is allocated to this data channel. c) 6 x 256 -Kbit/s and 8 x 64 Kbit/s data channels. Eight DWORDs of the buffer are allocated to each of the 6 data channels with 256 Kbit/s and two DWORDs are assigned to each of the 8 data channels with a transmission rate of 64 Kbit/s. The choice of the individual buffer size of each data channel can be made in the channel specification (shared memory). The buffer size of one channel is changeable without disturbing the transmission of the other channels.
CD
Active Transmit Channel (internal)
Used as Address Offset for TB
TF
Unused ITBS of Channel ITBS of Channel TB ITBS of Channel ITBS of Channel X1 X0 X2 X3
ITD04396
64 Long Words
Figure 16
Partitioning of TB
Data Sheet
57
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles The receive buffer (RB) is a FIFO buffer and has also a size of 64 DWORDs, which allows storing the data of eight complete PCM frames before transferring to the shared memory.
CD
Stored in RB together with Data/Status Word from RD
Active Receive Channel (internal)
RD
RB
64 Long Words
ITD04447
Figure 17
Partitioning of RB
The data transfer to the shared memory is performed via a 32-bit PCI interface. Figure 18 shows the division of the shared memory required for each MUNICH32X when using the serial PCM interface: - Configuration start address located at a programmable address in CCBA register - Control and Configuration Block (CCB) - Several interrupt circular queues with variable size for PCM Rx, PCM Tx, LBI Rx, LBI Tx, and peripherals on SSC, IOM(R)-2 - Descriptor and data sections for each channel Note that the LBI Control and Configuration Block (LCCB) differs from the CCB. Please refer to Chapter 12.1.2.
Data Sheet
58
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles
Receive DATA Receive Descriptor Transmit DATA Transmit Descriptor Receive DATA Receive Descriptor Transmit DATA Transmit Descriptor Receive DATA Receive Descriptor Transmit DATA Transmit Descriptor Receive DATA Receive Descriptor Transmit DATA Transmit Descriptor
Receive DATA Receive Descriptor Transmit DATA Transmit Descriptor Receive DATA Receive Descriptor Transmit DATA Transmit Descriptor Receive DATA Receive Descriptor Transmit DATA Transmit Descriptor Receive DATA Receive Descriptor Transmit DATA Transmit Descriptor
MUNICH32X
#0
ACTION SPEC. Reserved Time-Slot Assignment Channel 0 spec.
CCBA Register Control Start Address Control and Configuration Block (CCB)
Receive Descriptor Transmit Descriptor
Channel 31 spec. Current Receive Descriptor Address 0...31 Current Transmit Descriptor Address 0...31 #1 ACTION SPEC. Reserved Time-Slot Assignment Channel 0 spec. CCBA Register Control Start Address Control and Configuration Block (CCB)
Receive Descriptor Transmit Descriptor
Channel 31 spec. Current Receive Descriptor Address 0...31 Current Transmit Descriptor Address 0...31 #2 ACTION SPEC. Reserved Time-Slot Assignment Channel 0 spec. CCBA Register Control Start Address Control and Configuration Block (CCB)
Receive Descriptor Transmit Descriptor
Channel 31 spec. Current Receive Descriptor Address 0...31 Current Transmit Descriptor Address 0...31 #3 ACTION SPEC. Reserved Time-Slot Assignment Channel 0 spec. CCBA Register Control Start Address Control and Configuration Block (CCB)
Receive Descriptor Transmit Descriptor
Channel 31 spec. Current Receive Descriptor Address 0...31 Current Transmit Descriptor Address 0...31
ITD10413
Figure 18
Memory Division (Serial PCM Core) for up to four MUNICH32X
Note: To reduce complexity, the interrupt queues are not shown here.
Data Sheet
59
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles The shared memory allocated for each TX and Rx channel is organized as a chaining list of buffers set up by the host. Each chaining list is composed of descriptors and data sections. The descriptor contains the pointer to the next descriptor, the start address and the size of a data section. It also includes control information like frame end indication, transmission hold and rate adaption with interframe time-fill. In the transmit direction the MUNICH32X reads a Tx descriptor, calculates the data address, writes the current Tx descriptor address into the CCB, and fills the on-chip Tx buffer. When the data transfer of the specified section is completed, the MUNICH32X releases the buffer, and branches to the next Tx descriptor. If a frame end is indicated, the HDLC, TMB or TMR frame will be terminated and a specified number of the interframe time-fill bytes will be sent in order to perform rate adaption. If frame end is found in a Tx descriptor of a TMA channel, the specified number of programmable TMA flags is appended to the data in the descriptor. If frame end is found in a Tx descriptor of a V.110/X.30 channel, the frame is aborted (after the data in the descriptor are sent) by finishing the current 10-octet frame with `zeros' and sending 2 more 10-octet frames with `zeros' which leads to a loss of synchronism on the peer side. An adjustment for the inserted zeros in HDLC is programmable, which leads to a reduction of the specified number of interframe time-fill by 1/8th of the number of zero insertions. This can be used to send long HDLC frames with a more or less fixed data rate in spite of the zero insertions. A maskable interrupt is generated before transmission is started again.
Data Sheet
60
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles Examples of Typical Transmit Situations for the Individual Modes (refer to Chapter 12.1 ... Chapter 12.9) Note: These examples apply only to situations in which the MUNICH32X is operated in MUNICH32 mode, i.e. TXPOLL.POLLn bit field for channel n is reset, while the MODE2.HPOLL bit field is set. Variable Size Frame Oriented Protocols (HDLC, TMB, TMR) Normal operation, handling of frame end (FE) indication and hold (HOLD) indication. Note: 1. FNUM0 must be set to zero. 2. Flag = 7EH for HDLC 00H for TMB, TMR IC = 7EH for HDLC and IFTF = 0 FFH for HDLC and IFTF = 1 00H for TMB, TMR 3. After sending the FNUM2 - 1 IC characters the device starts polling the HOLD bit in the Tx descriptor once for each further sent IC character. It also reads again the pointer to the next Tx descriptor once with each poll of the hold indication. The pointer to the next transmit descriptor can be changed while HOLD = 1 is set. The value of the pointer, which is read in each poll where HOLD = 0, is used as the next descriptor address. If more than 6 IC characters will be sent, the use of the slow poll option provided in TXPOLL register should be considered as an alternative to using the descriptor HOLD bit, or polling should be avoided with a new mode. Please refer to Section 11.2.2 for a detailed description of the polling mechanism.
Data Sheet
61
2001-02-14
Figure 19
Data Sheet
Flag, C, ... , C Flag Frame ( Data 3 ) Frame ( Data 4 ) FNUM2 Flag, C , C C, C , C , C , Flag FNUM1+1
... ...
Poll HOLD=1? Poll HOLD=0
Flag
Frame (Data 1, Data 2)
...
...
...
FE=0 FNUM0 HOLD=0
FE = 1 FNUM1 HOLD=0
FE =1 FNUM2 HOLD=1
TxDescriptors Next TxDescr. Next TxDescr.
Handling of FE and HOLD Condition (Variable Size Frame Oriented Protocols)
....
Data 2 Data 3 Data 4
ITD10414
62
Next TxDescr.
Data 1
Data Sections
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles Fixed Size Frame Oriented Protocols (V110/X.30) Normal operation, E, S, X change (indicated by the V.110-bit in the transmit descriptor) Example for TRV = `11' Note: 1. FNUM must be 0 for all transmit descriptors. 2. The actual E-, S-, X-bits have to be in the first transmit descriptor after reset. 3. As shown in the example the contiguous parts of a data section belonging to one descriptor are sent in contiguous frames (DATA 1(1) are the bytes 0 - 3 of DATA 1, DATA 1(2) are the bytes 4 - 7 of DATA 1). If the end of a data section is reached within a frame, the frame is continued with data from the next data section belonging to a transmit descriptor with the bit V.110 = 0 (DATA 2(2) = byte 4 of DATA 2, DATA 3(1) = byte 0 - 2 of DATA 3). 4. The E-, S-, X-bits are only changed from one frame to the next not within a frame. The change occurs in the first frame which does not contain data of the previous data section. 5. Neither FE nor HOLD may be set to 1 during a normal operation of the mode. They both lead to an abort of the serial interface.
Data Sheet
63
2001-02-14
Figure 20
Data Sheet
Frame ( E, S, X, Data 2 (1) ) 10 Octets 10 Octets 10 Octets Frame ( E, S, X, Data 2, (2) Data 3 (1) ) Frame ( E, S, X, Data 3(2) )
...00 10 Octets
Frame ( E, S, X, Data 1 (1) )
Frame ( E, S, X, Data 1 (2) )
...
10 Octets
FE = 0 NO = 2 HOLD = 0 FE = 0 NO = 9 HOLD = 0 V110 = 0
FE = 0 NO = 8 HOLD = 0 V110 = 0
FE = 0 NO = 5 HOLD = 0 V110 = 0
FE = 0 NO = 2 HOLD = 0 V110 = 1
Handling of E, S, X Changes (Fixed Size Frame Oriented Protocols)
64
Next Transmit Descr. Next Transmit Descr. Next Transmit Descr. Data 1 E, S, X, Data 2 Data 3
Transmit V110 = 1 Descriptors Next Transmit Descr.
Next Transmit Descr.
.....
E, S, X,
Data Sections
ITD10415
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles Fixed Size Frame Oriented Protocols (V.110/X.30) Handling of frame end (FE) indication Note: 1. FNUM must be `0' for all transmit descriptors. 2. The frame (E, S, X, DATA 2(2)) is the beginning of a 10-octet frame. It stops with the octet no. y, containing the last data bit of DATA 2 to be sent. 3. Since y = 1, ..., 10 the 20 + y times 00H characters sent afterwards cause the peer station to recognize 3 consecutive 10-octet frames with frame error which leads to a loss of synchronism in the peer station. 4. For y = 10 DATA 2 is identical to DATA 2(1) and 30 times 00H characters are sent after frame (E, S, X, DATA 1(2), DATA 2(1)). 5. The E-, S-, X-bits are supposed to be loaded by an earlier transmit descriptor in the example. A descriptor changing them (with V.110-bit set) can be put between, before or after the descriptors in the example. It will change these bits according to the rules discussed previously.
Data Sheet
65
2001-02-14
Figure 21
Data Sheet
(1)
...
) Frame ( E, S, X, Data 1 , Data 2 10 Octets y=1,...,10 10-y Octets 10 Octets 20+y Octets
(2) (1)
Frame ( E, S, X, Data 1
) Frame ( E, S, X, Data 2
(2)
)
00,......,00 Frame ( E, S, X, Data 3
(1)
) ...
10 Octets
Transmit V110=0 Descriptors
FE=0 HOLD=0
FE = 1 HOLD=0 V110=0
FE=0 HOLD=0 V110=0
Handling of FE Condition (Fixed Size Frame Oriented Protocols)
66
....
Data 1
Data 2
Data 3
Data Sections
ITD10416
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
Figure 22
Data Sheet
00,......,00 00 00 10 Octets 20+y Octets ... 00 00 Frame ( E, S, X, Data 3 (1) ) . . . 10 Octets y=1,...,10 Poll HOLD=1? Poll HOLD=0 10-y Octets
FE=0 HOLD=0 V110=0
...
Frame ( E, S, X, Data 1
(1)
(2) (1) (2) ) Frame ( E, S, X, Data 1 , Data 2 ) Frame ( E, S, X, Data 2 )
Handling of hold (HOLD) indication
10 Octets
Fixed Size Frame Oriented Protocols (V110/X.30)
Transmit V110=0 Descriptors
FE=0 HOLD=0
FE = 1 HOLD=1 V110=0
Handling of HOLD Condition (Fixed Size Frame Oriented Protocols)
67
....
Data 2 Data 3
ITD10417
Data 1
Data Sections
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles Time Slot Oriented Protocol (TMA) Normal operation, handling of frame end (FE) indication and hold (HOLD) indication. Note: 1. FNUM must be set to zero. 2. TC = FFH for TMA and FA = 0 the programmed flag with TMA and FA = 1 3. After sending the FNUM2 - 1 IC characters the device starts polling the HOLD bit in the Tx descriptor once for each further sent IC character. It also reads again the pointer to the next Tx descriptor once with each poll of the hold indication. The pointer to the next transmit descriptor can be changed while HOLD = 1 is set. The value of the pointer, which is read in each poll where HOLD = 0, is used as the next descriptor address. If more than 6 IC characters will be sent, the use of the slow poll option provided in TXPOLL register should be considered as an alternative to using the descriptor HOLD bit, or polling should be avoided with a new mode. Please refer to Section 11.2.2 for a detailed description of the polling mechanism.
Data Sheet
68
2001-02-14
Figure 23
Data Sheet
Send "1" until next TSP
Time-Slot Boundaries TC,..................,TC Data 3 Data 4 FNUM2 TC, TC, TC,........TC, TC FNUM1+1 TC, TC,.............TC,
... ...
...
...
...
...
... ...
Poll HOLD=1? Poll HOLD=0
TC
Data 1
Data 2
Handling of FE and HOLD Condition (Time Slot Oriented Protocol)
69
Next Transmit Descr. Next Transmit Descr.
FE=0 FNUM0 HOLD=0
FE = 1 FNUM1 HOLD=0
FE=1 FNUM2 HOLD=1
Transmit Descriptors
Next Transmit Descr.
....
Data 1
Data 2
Data 3
Data 4
Data Sections
ITD10418
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles An activated transmission hold (HOLD bit in descriptor) prevents the MUNICH32X from sending more data. If a frame end has not occurred just before, the current frame will be aborted and an interrupt generated. Afterwards, the interframe time-fill bytes will be issued until the transmission hold indication is cleared. There is a further transmit hold (TH) bit in the Channel Specification in Control and Configuration Block (CCB) in addition to the HOLD bit in the descriptor. Setting the transmit hold (TH) bit by issuing a channel command will prevent further polling of the transmit descriptor. This transmit hold bit is interpreted in the Formatter Controller CD (see Figure 5); it causes the Transmit Formatter (TF) to stay in the idle state and to send interframe timefill after finishing the current frame. In the case of a very short frame (< ITBS), this frame will stay in the TF and not be sent until TH is removed. (In case of X.30/V.110 the current frame is aborted). This means that the Transmit Buffer (TB) is not emptied from the TF side after the current frame, but still requests further data from the shared memory until it is filled. On the other hand, in the case of the descriptor HOLD bit set, the TF empties the TB and no further data requests from the shared memory occur until HOLD is withdrawn. Then TB is filled again and the TF is activated only after enough data have been stored in the TB to prevent a data underrun.
Data Sheet
70
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles Reaction to Transmit HOLD for the Different Modes Variable Size Frame Oriented Protocols (HDLC, TMB, TMR) Reaction to a channel specification containing TH = 1 Normal operation Note: 1. IC = 7EH for HDLC and IFTF = 1 FFH for HDLC and IFTF = 0 00H for TMB or TMR 2. flag = 7EH for HDLC 00H for TMB or TMR 3. FNUM2 is ignored. The number of interframe time-fills sent between the first frame and the second frame solely depends on the internal action request initiated by setting bit CMD.ARPCM = 1 and leading to the action with TH = 0. 4. The times t1 and t2 are statistical but typically only a few clock cycles. 5. The TH bit (as all channel commands) is not synchronized with TB! (as opposed to the HOLD-bit in the descriptor). TH acts on the frame currently being sent, not necessarily on the last frame currently stored in the TB. In the example, TB may or may not have stored DATA 3 before the action request with TH = 1 was issued. See Chapter 12.6 for a further discussion of this issue. 6. If TH is handed over to CD outside of a frame, TH = 1 prevents the MUNICH32X from sending the next frame.
Data Sheet
71
2001-02-14
Figure 24
Data Sheet
t1 TH=1 in the Channel Specification handed over from DMAC to CD t2 TH=0 in the Channel Specification handed over from DMAC to CD
Action Request
.... ....
C, Flag Frame ( Data 3 ) . . .
Flag Frame ( ..., Data 1 , Data 2 ) Flag, C,
Handling of TH Condition (Variable Size Frame Oriented Protocols)
72
FE = 1 FNUM2 HOLD=0
FE=0 HOLD=0
... ....
Data 1
Data 2
Data 3
ITD10419
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles Fixed Size Frame Oriented Protocol (V.110/X.30) Reaction to a channel specification containing TH = 1 Normal operation Note: 1. The times t1 and t2 are statistical but typically only a few clock cycles. 2. The current processed frame is aborted, when TH = 1 is handed over to CD; only 10 - y, (y = 1, ..., 10) octets of it are sent. The device then starts to send 20 + y 00H characters regardless of how fast the TH bit is withdrawn. This ensures that the peer site is informed about the abort with a loss of synchronism. 3. The data section DATA 1 is split in the example; DATA 1(1) is sent in the aborted frame, all bits that were read into the MUNICH32X with the same access are discarded (they would have been sent in the next frame(s) if TH = 1 was not issued) and the device starts the next frame with the bits DATA 1(3) of the access to DATA 1 that follows the one getting the bits of DATA 1(1). 4. The TH (as all channel commands) is not synchronized with the Transmit Buffer. TH acts on the frame currently sent, not neccesarily on the last stored data. 5. No frame will start, if TH is handed over to CD before a frame has started (after an abort or after a reset).
Data Sheet
73
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles
Action Request t1 TH=1 in the Channel Specificaton handed over from DMAC to CD 00 . . . 00 ...... 20+y Octets t 2 TH=0 in the Channel Specificaton handed over from DMAC to CD 00 . . . 00 Frame ( E, S, X, Data 1 (3) ) . . . 10 Octets
. . . Frame ( E, S, X, Data 1 (1) ) 10-y Octets
...
FE=0 HOLD=0
....
Data 1
ITD10420
Figure 25
Handling of TH Condition (Fixed Size Frame Oriented Protocols)
Time Slot Oriented Protocol (TMA) Reaction to a channel specification containing TH = 1 Note: 1. TC is the programmed TFLAG for FA = 1 FFH for FA = 0 2. The times t1 and t2 are statistical but typically only a few clock cycles. 3. The TH bit (as all channel commands) is not synchronized with the TB! (as opposed to the HOLD-bit in the descriptor) TH acts to the data stream currently sent.
Data Sheet
74
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles
TH=0 in the Channel Specification handed over from DMAC to CD
TC, TC, TC, Data 3 . . .
....
t2
TH=1 in the Channel Specification handed over from DMAC to CD
....
Data 1, Data 2 , TC,
t1
FE = 1 HOLD=0
Time-Slot Boundaries
Action Request
FE=0 FNUM0 HOLD=0
Figure 26
Handling of TH Condition (Time Slot Oriented Protocol)
Variable Size Frame Oriented Modes (HDLC, TMB, TMR) Reaction to a channel specification containing TH = 1 Silencing of poll cycles for HOLD. Note: An action request initiated by setting bit CMD.ARPCM = 1 for an action specification leading to TH = 1 should be issued after (ITBS + 2) polls of the MUNICH32X, where ITBS is the previously programmed number of DWORDs in the TB reserved for this channel.
Data Sheet
75
...
Data 1
Data 2
Data 3
ITD10421
2001-02-14
Figure 27
Data Sheet
t1 TH=1 in the Channel Specification handed over from DMAC to CD t2 TH=0 in the Channel Specification handed over from DMAC to CD
Action Request
....
C, . . . C, ... Poll HOLD=1? No Poll Poll HOLD=1? Poll HOLD=0 ...
Flag Frame ( ..., Data 1 ) Flag, C, ... , C,
....
C, C, C , . . . C, Flag Frame ( Data 2 ) . . .
FNUM0
Handling of TH and HOLD Condition (Variable Size Frame Oriented Protocols)
....
Data 1 Data 2
ITD10422
76
...
FE=1 FNUM0 HOLD=1
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles Fixed Size Frame Oriented Protocol (V110/.30) Silencing of poll cycles by TH = 1 Note: 1. The times t1 and t2 are statistical but typically only a few clock cycles. 2. The TH bit (as all channel commands) is not synchronized with TB! (as opposed to the HOLD-bit in the descriptor) TH acts to the data stream currently sent. 3. In the example the proper use to silence a channel polling the HOLD bit of the transmit descriptor is illustrated. An action request initiated by setting bit CMD.ARPCM = 1 is issued after the polling has started and the HOLD-bit is not reset before polling has stopped by the TH bit. 4. An action request initiated by setting bit CMD.ARPCM = 1 for an action specification leading to TH = 1 should be issued after (ITBS + 2) polls of the MUNICH32X, where ITBS is previously programmed number of DWORDs in the TB reserved for this channel.
Data Sheet
77
2001-02-14
Figure 28
Data Sheet
t 1 TH=1 in the Channel Specif. handed over to CD t 2 ...... 00 . . . 00 Frame ( E, S, X, Data 2 (1) ) . . . 10 Octets No Poll Poll HOLD=1 HOLD=1 Poll HOLD=1 HOLD=0 20+y Octets TH=0 in the Channel Specif. handed over from DMAC to CD Frame ( E, S, X, Data 1 (2) ) 00 . . . 00 10-y Octets
Action Request
Frame ( E, S, X, Data 1 (1) )
10 Octets
Handling of TH and HOLD Condition (Fixed Size Frame Oriented Protocols)
....
Data 2
ITD10423
78
...
FE=1 HOLD=1
Data 1
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles Time Slot Oriented Protocol (TMA) Reaction to a channel specification containing TH = 1 Note: 1. TC = FFH for TMA and FA = 0 the programmed flag for TMA and FA = 1 2. FNUM2 is ignored. The number of interframe time-fills between the first frame and the second frame solely depends on the action request initiated by setting bit CMD.ARPCM = 1 leading to the action with a channel specification with TH = 0. 3. The times t1 and t2 are statistical but typically only a few clock cycles. 4. The TH bit (as all channel commands) is not synchronized with TB (as opposed to the HOLD-bit in the descriptor) TH acts on the data stream currently sent not neccessarily on the last data stored in TB. In the example TB may or may not have stored DATA 3 before action request with TH = 1 was issued. 5. The data stream is stopped and TC sent after the last byte of DATA 2 is sent. The stopping is triggered by the FE = 1 bit in the descriptor. 6. If TH is bonded over to CD during interframe time-fill (TC) it prevents the MUNICH32X from sending further data afterwards. 7. An action request initiated by setting bit CMD.ARPCM = 1 for an action specification leading to TH = 1 should be issued after (ITBS + 2) polls of the MUNICH32X, where ITBS is the previously programmed number of DWORDs in the TB reserved for this channel.
Data Sheet
79
2001-02-14
Figure 29
Data Sheet
t1 TH = 1 in the Channel Specification handed over from DMAC to CD t2 TH = 0 in the Channel Specification handed over from DMAC to CD
Action Request
.... ....
TC, TC, TC, . . . TC, ... No Poll Poll HOLD = 1? Poll HOLD = 0 Data 2 . . .
. . . Data 1, TC, TC, . . . TC, TC, . . . TC, ... Poll HOLD = 1?
FNUM0
Handling of TH and HOLD Condition (Time Slot Oriented Protocol)
80
... ....
FNUM0 FE = 1 HOLD = 1
Data 1
Data 2
ITD10424
Basic Functional Principles
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles In receive direction, the MUNICH32X reads a receive descriptor, calculates the data address, writes the current receive descriptor address into the CCB, and exchanges data between the on-chip receive buffer and the external memory. After the data section has been filled, the MUNICH32X writes the number of stored bytes (BNO) into the descriptor. If a frame end has occurred, the frame status is written into the descriptor and an interrupt is generated. The frame status includes the CRC check results and transmission error information like - - - - - `non octet of bits' (NOB), `aborted frame' (RA), `data overflow' (ROF), `maximum frame length exceeded' (LFD) and `frames with less than or equal the CRC length, which equals 2 bytes for CRC16 and 4 bytes for CRC32' (SF).
An activated reception-hold in the descriptor prevents the MUNICH32X from processing the receive data. The incoming frames are discarded until the hold is deactivated. Because the MUNICH32X is divided into two non-synchronized parts by the on-chip buffers, two different kinds of aborting a channel transmission are implemented. - Normal abort: This abort of a receive or transmit channel is processed in the formatters of the serial interface. The interframe time-fill code is sent after aborting the current issued frame. No accesses to the on-chip buffers are carried out, until the abort is withdrawn. The handling of the link lists and the processing of the buffers by the DMA controller are not affected by normal abort. - Fast abort: A fast abort is performed by the DMA controller and does not disturb the transmission on the serial interface. If this abort is detected the current descriptor is suspended with an abort status immediately followed by a branching to the new descriptor defined in the channel specification of the CCB. For initialization and control, the host sets up a Control and Configuration Block (CCB), including the action specification, time slot assignment and the channel specification. The host initiates an action, e.g. reconfiguration, change of the channel mode, reset or switching of a test loop by updating the CCB and issuing an action request. This is done by writing a `1' to the CMD.ARPCM bit field in Command register for the serial PCM core, or by writing a `1' to the CMD.ARLBI bit field for LBI related action requests. When the action request is detected by the MUNICH32X, it reads the control start address in CCBA register, then the action specification and (if necessary) additional information from the CCB. After execution, the action request is acknowledged by the STAT.PCMA or STAT.LBIA interrupt bit fields in Status register. MUNICH32X indicates an interrupt by activating the interrupt line and storing the interrupt information (including the corresponding channel number) in the associated interrupt queue, which is indicated by a flag in Status register STAT. Interrupts may be masked in Interrupt Mask register IMASK.
Data Sheet 81 2001-02-14
PEB 20321 PEF 20321
Basic Functional Principles The interrupt queues are implemented as circular buffers; the MUNICH32X starts to write status information into the queue and fills it successively in a circular manner. The host has to allocate sufficient buffer size and to empty the buffer fast enough in order to prevent overflow of the queue. Monitoring functions are implemented in MUNICH32X to discover errors or condition changes, i.e. - Receive frame end - Receive frame abort by overflow of the receive buffer or hold condition or recognized ABORT flag - Frame overflow, if a frame has to be discarded because of pending inaccessibility of the chip memory - Transmit frame end - Transmit frame abort (data underrun) by underrun of the transmit buffer or hold condition or bus cycle error - Change of the interframe time-fill. - Loss of synchronism or change of framing bits (V.110, X.30). - Short frame with no data content detected. An error or condition change is indicated by an interrupt. The host may react to the interrupt by either aborting or tristating the specific channel, or with a channel reconfiguration. To prevent underrun of the transmit buffer, sufficient buffer size has to be allocated to the channel. A more detailed discussion of the receive procedure with examples is provided under the detailed protocol description in Chapter 4.
Data Sheet
82
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
4
Detailed Protocol Description
In the following sections, the protocol support of the MUNICH32X is described in detail for transmit and receive direction. Each section starts with a discussion of the general features, then proceeds with protocol variants and options from the channel specification, and closes with a description of interrupts and special topics.
4.1
HDLC
Transmit Direction General Features In transmit direction - - - - the starting and ending flag (7EH before and after a frame) the interframe time-fill between frames the zero insertions (a `0'-bit after 5 consecutive `1's inserted within a frame) (optional) the Frame Check Sequence (FCS) at the end of a frame
is generated automatically. Options The different options for this mode are - the value of the interframe time-fill character in the channel specification: - 7EH for IFTF = 0 - FFH for IFTF = 1 - the number of interframe time-fill characters programmed by FNUM in the transmit descriptor. For the values FNUM = 0, 1, 2, the following sequences are used: - FNUM = 0: frame 1, 7EH, frame 2 (start flag = end flag) - FNUM = 1: frame 1, 7EH, 7EH, frame 2 - FNUM = 2: frame 1, 7EH, IC, 7EH, frame 2 - the correction of the number of interframe time-fill characters by 1/8 of the number of zero insertions by programming FA in the channel specification: - FA = 0: FNUM from the transmit descriptor is taken directly to determine the number of interframe time-fill characters as shown in Figure 29. - FA = 1: FNUM from the transmit descriptor is reduced by 1/8 of the number of the zero insertions of the frame corresponding to the transmit descriptor as shown in Figure 30. This allows transmission of long HDLC frames for a constant bit rate
Data Sheet
83
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
7 EH
Frame 1 x Zero Insertions
7 EH . . . . . . 7 EH Frame 2 y+1 x ], 0) 8
y= max (FNUM - [
FE=1
FNUM
Data Contents of Frame 1
Data Contents of Frame 2
ITD04579
Figure 30
FNUM Reduction in HDLC Transmit Mode
x x Note: 1. -- is the biggest integer smaller than -- . 8 8 x 2. For FNUM - -- < 0, y = 0 8
- the type of Frame Check Sequence (FCS) is determined by the CRC bit in the channel specification. CRC = 0: the generator polynomial x16 + 12 + x5 + 1 is used (2 byte FCS of CCITT Q.921) CRC = 1: the generator polynomial x32 + x26 + x23 +x22 + x16 + x12 + x11 + ... ... x10 + x8 + x7 + x5 + x4 + x2 + x + 1 (4 byte FCS) is used - the suppression of the automatic generation of the FCS is programmable in the channel specification: - CS = 0: FCS generated automatically CS = 1: FCS generation suppressed and in the transmit descriptor: CSM = 0: FCS generated automatically if CS = 0 in the channel specification CSM = 1: FCS generation suppressed
Data Sheet
84
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Interrupts The possible interrupts for the mode in transmit direction are: HI: FI: issued if the HI bit is detected in the transmit descriptor (not maskable) issued if the FE bit is detected in the transmit descriptor (maskable by FIT in the channel specification)
ERR: one of the following transmit errors has occurred: - the last descriptor had H = 1 and FE = 0 - the last descriptor had NO = 0 and FE = 0 (maskable by TE in the channel specification) FO: issued if the MUNICH32X was unable to access the shared memory in time either for new data to be sent or for a new transmit descriptor (maskable by TE in the channel specification) (maskable by FE2 in the channel specification) A typical data stream has the form: ... Example: HDLC channel with CS =0 (FCS generated automatically) INV = 0 (no inversion) CRC = 0 (CRC16) TRV = 00 (required as unused in HDLC mode) FA = 1 (flag adjustment) MODE = 11 (HDLC) IFTF = 1 (interframe time-fill `1's) Little Endian Data Format Channel number 1A ITF FLAG DATA FCS FLAG ITF ...
FE2: - data has been sent on the TXD line.
Data Sheet
85
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
Generate FI, HI-Int. 2000181A 1st Desc 31 0 A0010002 2 nd Desc 31 0 80060801
Generate FI-Int. 2000081A 3 rd Desc 31 0 80030800
Generate FI-Int. 2000081A
31
0 AA FE = 1 HOLD = 0 HI = 0 NO = 6 CSM = 1 FNUM = 1
31 0 FF FF FF FF 00 FF
31 Address
0 FA 28 AA
FE = 1 HOLD = 0 HI = 1 NO = 1 CSM = 0 FNUM = 2 Time Increases FLAG DATA 1
1
FE = 1 Increases HOLD = 0 HI = 0 NO = 3 CSM = 1 FNUM = 0 Zero Insertion
FCS
2
FLAG
ITF
3
..... 01111110 01010101 00010100010111110 01111110 11111111 8 Zero Insertion FLAG DATA 2
4
FLAG
5
01111110 111110111110111110111110111110111110111110111110 00000000 01111110 Zero Insertion DATA 3 FLAG
ITD10425
0101010100010100010111110 01111110
Figure 31
Example of HDLC Transmit Mode
Note: 1. Data is transmitted according to 2.8 of CCITT recommendation Q.921 2. Note: FCS in the data section is formatted as ordinary data!!! FCS is generated here automatically as CS = 0 and CSM = 0 for the 1st descriptor.
3. There was 1 zero insertion in the 1st frame, so FNUM - -- = FNUM = 2. 8 Therefore between the first and the second frame we have the sequence `FLAG ITF FLAG' (ITF = FFH because IFTF = 1). 1
4. No FCS is generated here as CSM is `1' for the second and third transmit descriptor. The FCS is supposed to be the last 2 bytes to be transmitted in this case, their validity is not checked internally.
Data Sheet 86 2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description 5. There were 8 zero insertions in the 2nd frame, so FNUM - Therefore between the second and the third frame we have a shared FLAG.
8 -8
= FNUM-1 = 0.
For CS = 1 (CRC select) the transmitted data stream would differ at FCS, FCS would just be omitted. For INV = 1 (channel inversion) all bits of the data stream (including FLAG, DATA, FCS, ITF) would be inverted. For CRC = 1 (CRC 32) the transmitted data stream would only differ in the FCS, the FCS would be 1101 0111 1010 0101 1000 0000 0010 0111. For FA = 0 (no flag adjustment) the transmitted data stream would change only after DATA 2. The value FNUM = 1 in the second descriptor would alone determine the number of interframe time-fill characters, the scenario would look like FLAG DATA 3
DATA 2
FLAG
0111 1110 0111 1110 For IFTF = 0 (ITF flags) the transmitted data stream would only differ at ITF, the 8 ones would be replaced by 0111 1110. In big endian mode the only difference is in the data section For the first descriptor it ought to be 31 AA and for the second 31 FF 00 and for the third 31 AA 28 FA 0 0 0
FF FF FF FF
Data Sheet
87
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Receive Direction General Features In receive direction: 1. The starting and ending flag (7EH before and after a frame) is recognized and extracted. 2. A change of the interframe time-fill is recognized and reported by an interrupt. 3. The zero insertions (a `0'-bit after five `1's within a frame) are extracted. 4. The FCS at the end of a frame is checked, it is (optionally) transferred to the shared memory together with the data. 5. The number of the bits within a frame (without zero insertions) is checked to be divisible by 8. 6. The number of bytes within a frame is checked to be smaller than MFL + 1 (after extraction of `0' insertions). The check is maskable by setting the bit field MFLD in MODE1 register. 7. The number of bits within a frame after extraction of `0' insertions is checked to be greater than check a) 16 for CRC = 0 32 for CRC = 1 (only for CS = 0) check b) 32 for CRC = 0 48 for CRC = 1. 8. The occurrence of an abort flag (7FH) ending a frame is checked. More detailed description of the individual features: 1. a. A frame is supposed to have started if after a sequence of 0111 1110 in the receive data stream neither FCH nor FDH nor 7EH has occurred. The frame is supposed to have started with the first bit after the closing `0' of the sequence. b. A frame is supposed to have stopped if a sequence of 0111 1110 or 0111 1111 is found in the data stream after the frame has started. The last bit of the frame is supposed to be the bit preceding the `0' in the above sequences. The cases of sequences 0111 1110 1111 111 and 0111 1110 0111 1111 are also supposed to be frames of bit length - 1 and 0 respectively. A frame is also supposed to have stopped if more than MFL bytes were received since the start of the frame. c. The ending flag of a frame may be the starting flag of the next frame (shared flags supported). 2. The receiver always remains in one of two possible interframe time-fill states: `F' and `O'. Figure 32 illustrates them. Note that a change from `F' to `O' and vice versa is reported by an IFC interrupt.
Data Sheet
88
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
RESET or Receive OFF Receive Initialize Channel Command O 011111101111110 or 0111111001111110 in the Data Stream (2 contiguous Flags received, Flags with shared Zeros supported) 111111111111111 in the Data Stream (15 contiguous "1"s received) or a Receive Abort Channel Command during 15 received Bits
ITD04577
F
Figure 32
Receiver Interframe Time-Fill States in HDLC
3. The `0' extraction is also carried out for the last 6 bits before the stopping sequence. 4. The last 16 (CRC = 0) or 32 (CRC = 1) bits of a frame (after extraction of the zero insertions are supposed to be the FCS of the remaining bits of the frame. (For the case of a frame with less than or equal to 16 or 32 bits, respectively, see point 7). The FCS is always checked, the check is reported in the CRCO bit of the last receive descriptor of the frame. CRCO = 1: FCS was incorrect CRCO = 0: FCS was correct 5. The check is reported in the NOB bit in the last receive descriptor of the frame NOB = 1: The bit length of the frame was not divisible by 8. NOB = 0: The bit length of the frame was divisible by 8. If NOB = 1: The last access to a receive data section of the frame may contain erroneous bits and should not be evaluated. 6. The check is reported in the LFD bit in the last receive descriptor of the frame (if MFLOFF = 0). LFD = 1: The number of bytes was greater than MFL. LFD = 0: The number of bytes was smaller or equal to MFL. Only the bytes up to the MFL + 1st one for CS =1 MFL - 1st one for CS = 0, CRC = 0 MFL - 3rd one for CS = 0, CRC = 1 are transferred to be stored memory. The bytes of the last access may be erroneous and should not be evaluated.
Data Sheet
89
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description 7. For frames not fulfilling check a) no data are transferred to the shared memory irrespective of CS. Only an interrupt with the bit FI, SF and (possibly) ERR is generated. For frames fulfilling check a) but not check b) data is transferred to the shared memory but the SF bit in the last receive descriptor is set. 8. The check is reported in the RA bit in the last receive descriptor of the frame RA = 1: The frame was stopped by the sequence 7FH RA = 0: The frame was not stopped by the sequence 7FH. Note: A receive descriptor with RA = 1 may also result from a fast receive abort or a receive abort channel command or from a receive descriptor with set HOLD bit. Options The different options for this mode are: - The kind of Frame Check Sequence (FCS) Two kinds of FCS are implemented and can be chosen by CRC bit. CRC = 0: the generator polynomial x16 + x12 + x5 + 1 is used (2 byte FCS of CCITT Q.921) CRC = 1: the generator polynomial x32 + x26 + x23 +x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 (4 byte FCS) is used. - the transfer of the FCS together with the received data is programmable by the CS bit. CS = 0: FCS is not transferred to the data section CS = 1: FCS is transferred to the data section. Note: FCS is always checked irrespective of the CS bit. Interrupts The possible interrupts for the mode in receive direction are: HI: FI: issued if the HI bit is detected in the receive descriptor (not maskable) issued if a received frame has been finished as discussed in 1.b of the protocol features (also for frames which do not lead to data transfer as discussed in 7. of the protocol features) (maskable by FIR in the channel spec.)
IFC: issued if a change of the interframe time-fill state as discussed in 2. has occurred. (maskable by IFC in the channel spec.) SF: a frame not fulfilling check a) has been detected (maskable by SFE in the channel spec.)
Data Sheet
90
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description ERR: issued if one of the following error conditions has occurred: - FCS was incorrect - the bit length was greater than MFL - the frame was stopped by 7FH - the frame could only be partly stored because of internal buffer overflow of RB - a fast receive abort channel command was issued - a receive abort channel command was detected during reception of a frame - a frame could only be partly transferred to the shared memory because of a receive descriptor with HOLD bit set (maskable by RE in the channel spec.) FO: issued if due to inaccessibility of internal buffer RB - one ore more complete frames have been lost - one ore more changes of interframe time-fill state were lost (maskable by RE in the channel spec.)
Note that all receive interrupts are maskable by setting the bit field RID in MODE1 register. Example: HDLC channel with CS = 1 (FCS transferred to shared memory) INV = 0 (no inversion) CRC = 1 (CRC 32) TRV = 00 (required as unused in HDLC mode) FA = x (irrelevant in Rx direction) MODE = 11 (HDLC) IFTF = x (irrelevant in Rx direction) Big Endian Data Format Channel No. 1D MFL = 10
Data Sheet
91
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
FLAG
1
DATA 1, FCS 1
. . . 01111110 0100 0011 1000 0101 1000 0000 1100 0000 1001 1100 0000 0001
2
DATA Ignored up to next Flag
10111100 0011 1101 0011 11100 0011 1000 0110 0011 1101 1011 0010 0100 Abort Sequence 01111111 Generate HI-Int. 3000101D 1st Desc 31 0 20080000 2 nd Desc 31 0 000C0000 Generate FI, ERR-Int. 3000091D
3
40080000 31 0 C2 A1 01 03 39 80 3D BC
C0031C00 31 CRCO, NOB, LFD 5 Last Access of a LFD Frame should be Ignored 0
DATA 2
4
ITD10426
Figure 33
Example of HDLC Receive Mode
Data Sheet
92
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
Zero Insertion FLAG DATA 2 01111110 0000 0000 0011 0101 1001 0010 1101 1111 0 Zero Insertion FCS 2 0000 0011 0010 0101 0100 1111 0101 1111 0 Zero Insertion DATA 3 (shared) FLAG 6 01111110 0000 0000 0011 0101 1001 0010 1101 1111 0 Zero Insertion Missing FCS 3 0000 0011 0010 0101 0100 1111 0101 1111 FLAG 01111110 Generate FI, HI-Int. 3000181D 3 rd Desc 31 0 200C0000 4 th Desc 31 0 000C0000 Generate FI, ERR-Int. 3000091D
C0080000 31 0 00 AC 49 FB C0 A4 F2 FA
C0081800 31 0 00 AC 49 FB DATA 3
DATA 2 FCS 2
CRCO, NOB
Last Access of a NOB Frame should be Ignored
ITD10427
Figure 34
Example of HDLC Receive Mode
Data Sheet
93
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
DATA 4
FCS 4
0101 0101 1101 1110 1010 0101 1000 0000 0010 0111 2 Flags with shared 0 FCS 5 0111 1110 111 1110 FLAG DATA 6 0000 0000 0000 0000 0000 0000 0000 0000 FCS 6
FLAG 01111110 Abort Sequence 01111111
01111110 0101 0101 1101 1110 1010 0101 1000 0000 0010 0111 DATA Ignored up to next Flag
7
15 x "1"
12
11111110101000110011100111010 0111 1111 1111 1111 01110011111100011111101111111 Generate FI-Int. 3000081D Generate IFC-Int. (2 Flags) 3000041D Generate short Frame Interrupt for FCS 5 30000A1D 5 th Desc 31 0 000C0000
9
10
Generate FI, ERR-Int. 3000091D Generate IFC-Int. 11 (15 x 1) 3000041D Generate Short Frame Interrupts 30000B1D
6 th Desc 31 0 00140000
C0050000 31 0 AA 7B A5 01 E4 XX XX XX
C0050200 31 0 AA 7B A5 01 E4 XX XX XX
ITD10428
DATA 4 FCS 4
8
RA
Figure 35
Example of HDLC Receive Mode
Note: 1. After Receive Initialization is detected all data are ignored until a flag is received. The receiver is in the interframe time-fill state `0'. 2. After MFL + 1 data bytes are received the further data are ignored (except for a change of the interframe time-fill state) and are neither stored in the RB nor reported to the shared memory. The receiver waits for the next flag. 3. Even the abort sequence at the end of the frame will not lead to the RA bit in the descriptor to be set. 4. Data are formatted according to 2.8 of CCITT Q.921. 5. The FCS is formatted as ordinary data!
Data Sheet
94
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description 6. LFD is issued and always accompanied by NOB. CRCO should not be interpreted for a LFD frame. 7. Here the ending flag of the second frame is the starting flag of the third frame. 8. After an abort sequence data is ignored until a flag is found (except for a change of the interframe time-fill state). They are neither stored in the RB nor reported to the shared memory. 9. The last 3 bytes in the last write access to the receive data section of the 5th descriptor have to be ignored. 10.The 2 flags with a shared 0 in the middle change the original interframe timefill state `0' of the receiver to `F'. The 2 flags following FCS 5 on the other hand do not change the interframe time-fill state, as it already was `F'. 11.The frame consisting only of 32 times 0 between 2 flags does not pass check a). It only leads to an interrupt. 12.The 15 x `1' leads to a change of the interframe time-fill state from `F' to `0' even through it is in a data ignored zone. 13.This frame of length - 1 leads to an interrupt. For CS = 0 (CRC not selected) the descriptors are shown in Figure 36.
Generate HI, FI, ERR-Int. 3000191D 1st Desc 1 31 0 20080000 3 rd Desc 2 31 0 200C0000
Generate HI, FI-Int. 3000181D
C0071C00 31 0 C2 A1 01 03
C0040000 31 0 00 AC 49 FB
Last Access of a LFD Frame should be Ignored
ITD10429
Figure 36
Example of HDLC Reception with CS = 0
Data Sheet
95
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
Generate FI, ERR-Int. 3000091D 4 th Desc 31 0 000C0000 5 th Desc 31 0 000C0000
Interrupts as in the original Example 6 th Desc 31 0 00140000
C0041800 31 CRCO, NOB 0
C0014000 31 0 AA XX XX XX
C0014200 31 0 AA XX XX XX
SF Last Access of a NOB Frame should be Ignored
SF, RA
ITD10430
Figure 37
Example of HDLC Reception with CS = 0
Note: 1. Only the 7 leading bytes are reported (the last 4 are supposed to be the FCS even in this case). 2. It is assumed here for convenience that the first descriptor points to the third and not to the second descriptor as in the original example.
Data Sheet
96
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description For INV = 1 (channel inversion), all bits of the data stream (including DATA, FCS, flag, abort sequence 15 x `1' ) are interpreted inversely, e.g. `1000 0001' would be interpreted as a flag, and 15 x `0' would lead to a change from interframe time-fill state `F' to `0' etc. For CRC = 0 (CRC 16), the correct FCS (e.g., zeros for DATA 4) would be 00001 0100 0101 1110. The 5th descriptor would then appear as shown below.
5 th Desc 31 0 000C0000
C0034000 31 0 AA 28 FA XX
ITD04570
In little endian mode, the only difference is in the receive data sections. They would be
of 1st Desc 31 0 03 01 A1 C2 BC 30 80 39
of 3 rd Desc 31 0 FB 49 AC 00 FA F2 A4 C0
of 5 th Desc 31 0 01 A5 7B AA XX XX XX E4
ITD04571
Data Sheet
97
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
4.2
TMB
Transmit Direction General Features In transmit direction: - The starting and ending flag (00H before and after a frame) - The interframe time-fill between frames is generated automatically. Options The different options for this mode are: - The number of interframe time-fill characters (as shown in Figure 27) by choosing FNUM in the transmit descriptor. For the values FNUM = 0, 1, 2, the following sequences are used: FNUM = 0: FNUM = 1: FNUM = 2: Interrupts The possible interrupts for the mode in transmit direction are identical to those of HDLC. A typical data stream has the form: (ITF DATA ITF DATA). Example TMB channel with INV = 0 (no inversion) CRC = 0 (required) TRV = 00 (required) FA = 0 (required) MODE = 01 (TMB) IFTF = 0 (required) Little Endian Data Format Channel number 5 ... frame 1, 00H, frame 2 ... (start = end flag) ... frame 1, 00H, 00H, frame 2 ... ... frame 1, 00H, 00H, 00H, frame 2 ...
Data Sheet
98
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
Generate HI-Int. 20001005
2
Generate FI-Int. 20000805
3
Generate FI-Int. 20000805
31 20020000
0
31 80000000
0
31
0
80030001
31
0 CE AB
31
0 45 23 01
1
FLAG ... 0 0
DATA 1 FLAG
DATA 2
2 FLAGS
ITD10431
D 5 7 3 0 0 8 0 C 4 A 2 0 0 0 0 ...
Figure 38
Example of TMB Transmission
Note: 1. Data is transmitted according to Q.921 2.8 and fully transparent. 2. A transmit descriptor with NO = 0 and FE = 1 is allowed, one with NO = 0 and FE = 0 is not allowed. 3. FNUM = 1 leads to 2 FLAGS after DATA 2.
Data Sheet
99
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Receive Direction General Features 1. The starting and ending flag (00H before and after a frame) as well as interframe timefill is recognized and extracted. 2. The number of bits within a frame is checked to be divisible by 8. 3. The number of bytes within a frame is checked to be smaller than MFL + 1. 4. A frame containing less than 8 bits may be ignored completely by the receiver. More detailed description of the individual features: 1. a. A frame is supposed to have started if after a sequence `0000 0000' a `1'-bit is recognized. The frame is supposed to have this `1'-bit as first bit. b. A frame is supposed to have stopped if - either a sequence 0000 0000 1 is found in the data stream after the frame has started - or a sequence 0000 0000 is found octet synchronous (i.e. the first bit of the sequence 00H is the 8 m + 1st bit since the starting `1'-bit of 1.a. for an integer m). In both cases the last bit before the sequence 00H is supposed to be the last bit of the frame. 2. The check is reported in the NOB bit in the last receive descriptor of the frame. NOB = 1: The bit length of the frame was not divisible by 8. NOB = 0: The bit length of the frame was divisible by 8. 3. The check is reported in the LFD bit in the last receive descriptor of the frame. LFD = 1: The number of bytes was greater than MFL. LFD = 0: The number of bytes was smaller or equal to MFL. Only the bytes up to the MFl + 1st one are transferred to the shared memory. The bytes of the last access to the receive data section of the frame may contain erroneous bits and shouldn't be evaluated. LFD is always accompanied by NOB. Options There are no options in receive direction for this mode.
Data Sheet
100
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Interrupts The possible interrupts for the mode in receive direction are: HI: FI: issued if HI bit is detected in the receive descriptor (not maskable). issued if a received frame has been finished as discussed in 1b) of the protocol features or a receive abort channel command was detected during reception of a frame. (maskable by FIR in the channel spec.)
ERR: issued if one of the following error conditions has occurred - the bit length of the frame was not divisible by 8 - the byte length was greater than MFL - the frame could only be partly stored because of internal buffer overflow of RB - a fast receive abort channel command was issued - the frame could only be partly transferred due to a receive descriptor with set HOLD bit. (maskable by RE in the channel specification) FO: issued if due to inaccessibility of the internal buffer RB one or more complete frames have been lost. (maskable by RE in the channel spec.)
Example: TMB channel with INV = 0 (no inversion) CRC = 0 (required) TRV = 00 (required) FA = 0 (required) MODE = 01 (TMB) IFTF = 0 (required) MFL = 7 Big Endian Data Format Channel No. A
Data Sheet
101
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
FLAG
1
DATA 1 10111001 10000000
octet synchronous FLAG
3
DATA 2 11001011
octet synchronous FLAG 00000000
DATA 3 10000000
00000000
00000000 00 (start) FLAG
non octet synchronous FLAG 10111100 0000000
4
DATA 4 10000000 11111110 01111111 11111011 11010101 01001100
5 DATA Ignored up to next Frame start FLAG
DATA 5 10101101 00101010
FLAG 0000 0000
10100000 11110111 01010101 0000 0000 0000
Generate FI-Int. 3000080A 1 st Desc 31 0 00040000 2 nd Desc 31 0 200C0000
Generate FI, HI-Int. 3000180A 3 rd Desc 31 0 20080000
Generate FI, HI, ERR-Int. 3000190A
C0020000 31 0 9D 01 XX XX
C0010000 31 0 DATA 2 D3 XX XX XX
C0020800 31 NOB DATA 3 Last Access of a NOB Frame should be Ignored
ITD10432
0
DATA 1
2
Figure 39
Example of TMB Reception
Data Sheet
102
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
Generate HI-Int. 3000100A 4 th Desc 31 0 20080000 5 th Desc 6 31 0 00040000
Generate FI, ERR-Int. 3000090A 6 th Desc 31 0 00FC0000
Generate FI-Int. 3000080A
40080000 31 0 01 7F FE DF
C0000C00
C0020000 31 0 B5 54 XX XX
DATA 4
LFD, NOB
DATA 5
Last Access of a LFD Frame should be Ignored
ITD10433
Figure 40
Example of TMB Reception
Note: 1. After Receive Initialization is detected all data are ignored until the starting sequence 0000 0000 1 is detected. 2. Data are formatted according to 2.8 of CCITT Q.921. 3. The octet synchronous (end) flag of one frame can be part of the (start) flag of the next frame. Between DATA 1 and DATA 3 they are identical (shared flags supported). 4. Here the sequence 0000 0000 1 is detected non-octet synchronously. Therefore the frame belonging to DATA 3 is supposed to have ended non-octet synchronously (NOB set in the 3rd descriptor). 5. After MFL + 1 data bytes the further data are ignored and are neither stored in the RB nor reported to the shared memory. The receiver waits for the next sequence 0000 0000 1 to come. 6. If a receive descriptor is full (4th desc.) the MUNICH32X branches to the next receive descriptor (5th desc.) even if no further data are to be given to the shared memory.
Data Sheet
103
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description For INV = 1 (channel inversion) all bits of the data stream (including DATA, FLAG) are interpreted inversely, e.g., 1111 1111 0 would be interpreted as starting sequence. In little endian format the only difference is in the receive data sections. They would be
of 1st Desc 31 0 XX XX 01 9D
of 2 nd Desc 31 0 XX XX XX D3
of 4 th Desc 31 0 DF FE 7F 01
of 6 th Desc 31 0 XX XX 54 B5
ITD05034
Data Sheet
104
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
4.3
TMR
Transmit Direction General Features In transmit direction - the starting and ending flag (00 00H or 0 00H between frames) is generated automatically. Options The different options for this mode are - the number of interframe time-fill characters as shown in Figure 19 by choosing FNUM in the transmit descriptor. For the values 0, 1, 2, the following sequences are used: FNUM = 0: FNUM = 1: FNUM = 2: ... frame 1, 000H, frame 2 ... ... frame 1, 00H, 00H, frame 2 ... ... frame 1, 00H, 00H, 00H, frame 2 ...
By choosing FNUM = 0 and setting the last transmitted nibble in the transmit data section to 0H frames of effective length n + 1/2 bytes can be sent as required by GSM 08.60. Interrupts The possible interrupts for the mode in the transmit direction are identical to those of HDLC. A typical data stream has the form: (ITF DATA ITF DATA) Example: TMR channel with INV = 0 (no inversion) CRC = 1 (required) TRV = 00 (required) FA = 0 (required) MODE = 01 (TMR) IFTF = 0 (required) Little Endian Data Format Channel No. 5
Data Sheet
105
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
Generate HI-Int. 20001005
2
Generate FI-Int. 20000805
3
Generate FI-Int. 20000805
31 20020000
0
31 80000000
0
31
0
80030001
31
0 0E AB
31
0 45 23 01
1
FLAG ... 0 0
DATA 1
FLAG
DATA 2
2 FLAGS
D 5 7 0 0 0 8 0 C 4 A 2 0 0 0 0 ...
ITD10434
Frame of Effective Length 1 1/2 Byte
Figure 41
Example of TMR Transmission
Note: 1. Data is transmitted according to Q.921 2.8 and fully transparent. 2. A transmit descriptor with NO = 0 and FE = 1 is allowed, one with NO = 0 and FE = 0 is forbidden. 3. FNUM = 1 leads to 2 FLAGS after DATA 2.
Data Sheet
106
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Receive Direction General Features 1. The starting and the ending flag (00 00H) is recognized. Interframe time-fill, both characters of the starting flag and the last character of the ending flag is extracted. 2. The number of bits within a frame is checked to be divisible by 8. 3. The number of bytes within a frame is checked to be smaller than MFL. More detailed description of the individual features 1. a. A frame is supposed to have started after a sequence of 16 zeros a `1'-bit is recognized. The frame is supposed to have this `1'-bit as first bit. b. A frame is supposed to have stopped if - either a sequence of 16 `zeros' and a `one' is found in the data stream after the frame has started - or a sequence of 16 zeros is found octet synchronous (i.e. the first bit of the sequence 00 00H is the 8m + 1st bit since the starting `1'-bit of 1.a. for an integer m). In both cases the eighth bit of the sequence 00 00H is supposed to be the last bit of the frame. 2. The check is reported in the NOB bit in the last receive descriptor of the frame. NOB = 1 the bit length of the frame was not divisible by 8. NOB = 0 the bit length of the frame was divisible by 8. If NOB = 1 the last byte of the last access to a receive data section of the frame may contain erroneous bits and shouldn't be evaluated. This does not affect the reception of frames with n + 1/2 octets 3. The check is reported in the LFD bit in the last receive descriptor of the frame. LFD = 1 the number of bytes was greater than MFL. LFD = 0 the number of bytes was smaller or equal to MFL. MFL + 1st one are transferred to the shared memory. The bytes of the last access to the receive data section of the frame may contain erroneous bits and should not be evaluated. LFD is always accompanied by NOB.
Data Sheet
107
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Options There are no options in receive direction for this mode. Interrupts The possible interrupts for the mode in receive direction are identical to those of TMB. Example: TMR channel with INV = 0 (no inversion) CRC = 1 (required) TRV = 00 FA = 0 MODE = 01 (TMR) IFTF = 0 (required) MFL = 7 Big Endian Data Format Channel No. 15
Data Sheet
108
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
(start) FLAG
1
DATA 1
octet synchronous (end) FLAG 2
DATA 2
octet synchronous FLAG
.... 00000000 00000000
10111001 10000000 00000000 00000000 0000 11001011 00000000 00000000 (start) FLAG DATA 3 non octet synchronous FLAG
3
10000000 00000000 10111100 11110101 11000000 00000000 0000 11110001 11011111 01011001 01101010
4 DATA Ignored up to next Frame start
DATA 4
DATA 5
octet synchronous (end) FLAG
11110011 11110111 11011101 11011011 11111111 00000000 00000000 11011101 01111010 00000000 00000000
Generate FI-Int. 30000815 1 st Desc 31 0 00040000 2 nd Desc 31 0 200C0000
Generate FI, HI-Int. 30001815 3 rd Desc 31 0 00080000
Generate FI, ERR-Int. 30000915
C0030000 31 0 9D 01 00 XX
C0020000 31 0 DATA 2 D3 00 XX XX
C0060800 31 0 01 00 3D AF 03 XX XX XX DATA 3 Last Byte of a NOB Frame should be Ignored
DATA 1
5
NOB
Generate HI-Int. 30001015 4 th Desc 31 0 20080000 5 th Desc 6 31 0 20040000
Generate HI, FI, ERR-Int. 30001915 6 th Desc 31 0 00080000
Generate FI-Int. 30000815
40080000 31 0 DATA 4 8F FB 9A 56
C0000C00
C0030000 31 0 DATA 5 BB 5E 00 XX
LFD, NOB
Last Access of a LFD Frame should be Ignored
ITD10435
Figure 42
Example of TMR Reception
Data Sheet
109
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description 1. After receive initialization is detected all data are ignored until a starting sequence (16 `zeros', `ones') is detected. 2. The octet synchronous (end) flag of one frame can be part of the (start) flag of the next frame. Note that the first 00H character of the end flag is stored in the receive data section as ordinary data and is included in BNO. Between DATA 2 and DATA 3 the start and end flag are identical (shared flags supported). 3. Here the start sequence is detected non-octet synchronously within a frame. Therefore the frame belonging to DATA 3 is supposed to have ended non-octet synchronously (NOB set in the 3rd descriptor). 4. After MFL + 1 data bytes the further data are ignored and are neither stored in the RB nor reported to the shared memory. 5. Data are formatted according to 2.8 of CCITT Q.921. 6. If a receive descriptor is full (4th descriptor) the MUNICH32X branches to the next receive descriptor (5th descriptor) even if no further data are to be given to the shared memory. For INV = 1 (channel inversion) all bits of the data stream (including DATA, FLAG) are interpreted inversely e.g. 16 `ones', `zeros' is interpreted as starting sequence then. In little endian mode the only difference is in the receive data sections. They would be
of 1st Desc 31 0 XX 00 01 01
of 2nd Desc 31 0 XX XX 00 D3
of 3rd Desc 31 0 AF 3D 00 01 XX XX XX 03
of 4th Desc 31 0 56 9A FB 8F
of 6 th Desc 31 0 XX 00 5E BB
ITD10436
Data Sheet
110
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
4.4
TMA
Transmit Direction General Features In the transmit direction - a frame-synchronous transparent data transmission - a programmable number of programmable fill characters after data is generated automatically. Synchronized Data Transfer In order to transfer data over a PCM interface with a bandwidth greater than 64 Kbit/s, multiple time-slots must be concatenated into a single channel. E.g., video applications require 2 to 6 and more time slots; depending on the picture quality. In such applications, it is mandatory to know when the MUNICH32X starts to send real data (not only the flags). The MUNICH32X supports fractional T1/PRI or full T1/PRI channels for high bandwidth services by synchronizing the START of the transparent data with the START of the 8 kHz frame. This allows complete T1 transparency end-to-end over the network. Consider the case of an originating end in which in-band control information is intended to be carried in time-slot 0. By synchronizing the outgoing (transparent stream) to the Frame sync pulse, the time slot integrity can be maintained all the way to the far end. For example, the time slots 0, 1, 5, 6, 21 and 23 are used for building a 384 Kbit/s data channel to be transferred via a fractional T1 interface (refer to Figure 43). As long as the MUNICH32X detects the HOLD bit = 1 (no transmit data is available) it transmits `FF'. Upon the detecting HOLD = 0 (in time slot 5) the MUNICH32X fetches data from shared memory and starts to transmit data in the first time slot of the assigned data channel in one of the next frames.
Data Sheet
111
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
Frame Sync 8 kHz Data Channel Transmit Data MUNICH32X
T1 Frame n Format Time Slots 0 1 2 3 4 5 6 7 ... 21 22 23
Frame n+1 0 1 ...
H=1 H=1 FF FF
H=0 FF FF
FF
FF
DB0 DB1
MUNICH32
FF
FF
FF
FF
DB0
DB1
DB2 DB3
ITD10343
'H': Tx descriptor HOLD bit field
Figure 43
Example of Data Transfer Synchronization in TMA mode
The MUNICH32X starts to transmit real data in the frame n + x. The value x depends on the size of the assigned transmit buffer (ITBS value in the Channel Specification) and on the bandwidth provided for transmission. Generally, the following rule applies: The smaller ITBS and the larger the bandwidth, the earlier the MUNICH32X starts to send data. For the above example, if ITBS was programmed to 12 DWORD, x would be 3. Thus the synchronized data transmission starts in the frame n + 3. If the MUNICH32X has to send multiple data frames terminated by a Frame End (without descriptor HOLD bit = `1' between the frames), it synchronizes the beginning of every data frame to the frame sync pulse. After the transmission of the last data frame byte the MUNICH32X sends inter-frame time fill flags (TFLAG programmed in the Channel Specification) according to the number programmed in the Transmit Descriptor (FNUM) Note: MUNICH32 starts to transfer data immediately after detecting HOLD = 0.
Data Sheet
112
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Options The different options for this mode are - The value of the fill-character can be programmed for FA = 1 in the channel specification. The fill-character (TC) is then programmed in the TFLAG. For FA = 0 the fill character is FFH and TFLAG has to be set to 00H. If subchanneling is chosen (not all fill/mask bits of the channel are `1') FA must be set to `0'. - The number of inter-data time-fill characters as shown in Figure 23. By setting the value of FNUM the following sequences result: FNUM = 0... DATA 1, TC, DATA 2 ... FNUM = 1... DATA 1, TC, TC, DATA 2 ... FNUM = 2... DATA 1, TC, TC, TC, DATA 2 ... - DATA 2 starts at synchronization pulse TSP; `1' are sent between last TC and DATA 2. - In case of using subchanneling by fill masks the MUNICH32X supports two different modes of operation in Transparent Mode A (TMA). These modes are selected by bit 'CRC' in the channel configuration. CRC = `0': Data is transmitted transparently only in bit positions selected by the transmit fill mask (corresponding fill mask bit equal `1'). Masked bit positions are driven Tristate `Z'. In receive direction bits are received from bit positions selected by the receive fill mask (corresponding fill mask bit equal `1') only. Receive data is grouped to octets and stored in memory transparently (no gaps). CRC = `1': In transmit direction each data octet is masked with the transmit fill mask. Masked bit positions are overwritten with Tristate `Z' when transmitted. In receive direction the receive fill mask has to be set to 0xFF. The entire 8 bit time slot is received and stored byte aligned in memory. It is the software responsibility to mask received data octets as needed by the application.
Data Sheet
113
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Interrupts The possible interrupts for this mode in transmit direction are identical to those of HDLC. Example 1: (no subchanneling by fill/mask bits) TMA channel with TFLAG = B2H INV = 0 CRC = 0 TRV = 00 FA = 1 MODE = 00 IFTF = 0
(no data inversion) (required) (flag filtering) (TMA) (required)
All fill-mask bits are `1' for this channel (no high impedance overwrite) Little Endian Data Format Channel no. D
TSP Time-Slot Boundaries Bit No TSP
0 70 70 70 70 70 70 70 70 70 70 70 70 DATA 1 ...
1
DATA 2
TC
2
DATA 3 2 TCs
DATA 4
D 5 8 B 6 C 4 8 0 0 B 2 4 F B 2 B 2 8 B B 4 4 C ...
Generate HI-Interrupt 2000100D 1 st Desc 31 0 20020000 0 2 nd Desc 31 0 A0030000 0
Generate HI-, FI-Interrupt 2000180D 3 rd Desc 31 0 80010001 0 4 th Desc 31 0 00030000 0
31 0 DATA 1 XX XX D1 AB
31 0 DATA 2 XX 00 12 36
31 0 DATA 3 XX XX XX F2
31 0 DATA 4 XX 32 2D D1
ITD10437
For INV=1 DATA and TC would be Inverted
Figure 44
Example of TMA Transmission
Data Sheet
114
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Note: 1. Data are formatted according to 2.8 of Q.921. The TC is transmitted MSB (bit 15) first though!!! 2. FNUM = 0 in the second descriptor leads to the insertion of the TC after DATA 2, FNUM = 1 in the third descriptor to the insertion of 2 TCs. 3. A sync-pulse defined number of `1' is inserted between `TC-DATA 3' and `TCDATA 4. For INV = 1 the data stream would be inverted completely: DATA 1 DATA 2 TC DATA 3 2 TCs DATA 4 ... 2A 74 93 B7 FF 4D B0 4D 4D 74 4B B3 ...
For FA = 0 TFLAG has to be programmed to 00H, resulting in a data stream of DATA 1 DATA 2 TC DATA 3 2 TCs 4F DATA 4
D5 8B 6C 48 00 FF
FF FF 8B B4 4C
In big endian mode, the data sections for the same data stream would have been
of 1st Desc 31 0 AB D1 XX XX
of 2nd Desc 31 0 36 12 00 XX
of 3 rd Desc 31 0 F2 XX XX XX
of 4 th Desc 31 0 D1 2D 32 XX
ITD05036
Data Sheet
115
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Example 2: (subchanneling by fill/mask bits) TMA channel with TFLAG = 00H (required for this case) INV = 0 (no data inversion) CRC = 0 TRV = 00 (required) FA = 0 (required for subchanneling) MODE = 00 (TMA) IFTF = 0 (required) Little Endian Data Format Channel no. D
Generate HI-Interrupt 2000100D 1 st Desc 31 0 20020000 0 2 nd Desc 31 0 A0030000 0
Generate HI-Interrupt 2000100D 3 rd Desc 31 0 80010001 0
Generate FI-Interrupt 2000080D 4 th Desc 31 0 00030000 0
31 0 DATA 1 XX XX D1 AB
31 0 DATA 2 XX 00 12 36
31 0 DATA 3 XX XX XX F2
31 0 DATA 4 XX 32 2D D1
ITD10438
Figure 45
Example of TMA Transmission
Data Sheet
116
2001-02-14
Figure 46
Data Sheet
012345670123456701234567012345670123456701234567 010011011111111100000000110111011110101100111111 111101111000101111111111011010100001010011111111 Z 1 Z Z 1 1 Z 1 0 1 1 1 1 0 0 0 Z Z Z Z Z Z Z Z 1 0 Z 1 1 1 Z 1 1 1 1 Z 1 Z 1 1 Z Z 0 1 1 0 1 0 ... DATA 1 (F7 8B) TC (FF) DATA 2 (6A 14)
ITD10449
Slot Boundaries
Bit No
Fill/Mask High Impedance
Internal Data
External Data (TXD)
117
012345670123456701234567012345670123456701234567 111011111011111011101111011110110011101101111111 010111111111111111111111100011111111010011001100 1 0 0 Z 0 0 1 0 1 Z 0 0 1 1 1 Z 1 1 1 Z 1 1 0 1 Z 0 1 1 1 Z 1 1 Z Z 1 1 1 Z 1 1 Z 1 1 1 1 1 1 1 ... DATA 2 (6A 14) TC (FF) DATA 3 (5F) 2 TCs (FF FF)
ITD10439
Slot Boundaries
Bit No
Fill/Mask High Impedance
Internal Data
External Data (TXD)
Detailed Protocol Description
PEB 20321 PEF 20321
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Receive Direction General Features In the receive direction - a slot synchronous transparent data reception - for FA = `1' a slot synchronous programmable flag extraction is performed automatically. Options The different options for this mode are: - the programmable character TC to be extracted for FA = `1' is TFLAG. For FA = `0' nothing is extracted. If subchanneling is chosen (not all fill/mask bits of the channel are `1') FA must be set to `0'. - In case of using subchanneling by fill masks the MUNICH32X supports two different modes of operation in Transparent Mode A (TMA). These modes are selected by bit `CRC' in the channel configuration. CRC = `0': Receive data is grouped to octets and stored in memory transparently (no gaps). CRC = `0': In receive direction the receive fill mask has to be set to 0xFF. The entire 8 bit time slot is received and stored byte aligned in memory. It is the software responsibility to mask received data octets as needed by the application. Interrupts The possible interrupts for the mode in receive direction are: HI: issued if the HI bit is detected in the receive descriptor (not maskable). ERR: issued if a fast receive abort channel command was issued. (maskable by RE in the channel spec.) FO: issued if data could only partially stored due to internal buffer overflow of RB. (maskable by RE in the channel spec.)
Data Sheet
118
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description Example 1: (no subchanneling) TMA channel with TFLAG = D7 INV = 0 (no channel inversion) CRC = 0 TRV = 00 (required) FA = 1 MODE = 00 (TMA) IFTF = 0 Big Endian Data Format Channel No. E
Slot Boundaries
0 70 70 70 70 70 70 70 70 70 70 70 7 D6 D7 AF BD 0 0 D7 D7 2 8 6 3 D7 7 D 7 8 Octet Synchr. TC 2 Octet Synchr. TCs Octet Not Synchr. Octet TC Synchr. TC not Filtered Generate HI-Interrupt 3000090E 31 00040000 0 31 20040000 0
40040000 31 0 6B F5 BD 00
40040000 31 0 14 C6 BE 1E
ITD10440
Figure 47
Example of TMA Reception
Note: The FE bit is never set in a receive descriptor. Data are formatted according to 2.8 Q.921. For FA = 0 (and therefore TFLAG = 00H), the descriptor would be
Data Sheet
119
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
Generate HI-Interrupt 3000090E 31 00040000 0 31 20040000 0 31 00040000 0
40040000 31 0 6B EB F5 BD
40040000 31 0 00 EB EB 14
40040000 31 0 C6 EB BE 1E
ITD10441
Figure 48
Example of TMA Reception
For INV = 1 the receiver filters the inverse of the TFLAG as TC out of the data stream and inverts the data (only the octet synchronous 28H would be filtered). In little endian mode, the data sections for the first descriptor would be: 00 BD F5 6B
and for the second descriptor: 1E BE C6 14
Data Sheet
120
2001-02-14
PEB 20321 PEF 20321
Detailed Protocol Description
4.5
V.110/X.30
Transmit Direction General Features In transmit direction - the synchronization pattern for V.110/X.30 frame as shown in Table 7. - the framing for the different data rates with programmable E-, S-, X-bits - sending `0' before all frames is performed automatically. Table 7 Octet No. 1 2 3 4 5 6 7 8 9 10 Synchronization Pattern for V.110/X.30-Frames 1 0 1 1 1 1 1 1 1 1 1 2 0 3 0 4 0 5 0 6 0 7 0 8 0
The E-, S-, X-bits are fed into the data stream by special transmit descriptor (as shown in Figure 20), they can only change from one 10-octet frame to the next, not within a 10octet frame. The data from the data sections are supposed to come in the form:
31 1 1 B6 B5 B4 B3 B2 B1 1 1 B12B11B10 B9 B8 B7 1 1 B18B17B16B15B14B13 1 0 1 B24B23B22B21B20B19
(in big endian mode)
31 1 1 B24B23B22B21B20B19 1 1 B18B17B16B15B14B13 1 1 B12B11B10 B9 B8 B7 1 0 1 B6 B5 B4 B3 B2 B1
(in little endian mode), where, in case of a transmission rate of 600 bit/s, for example B1 to B6 belong to the first 10-octet frame, B7 to B12 belong to the second 10-octet frame, etc.
Data Sheet
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Detailed Protocol Description Options The different options for this mode are: - the framing pattern, as shown in Table 8 to Table 11, is programmed by the bits TRV. Interrupts HI: issued if the HI bit is detected in the transmit descriptor (not maskable) ERR: if one of the following transmit errors has occurred - the last descriptor had FE = 1 (leads to an abort of the transmit data, see Figure 21) - the last descriptor had H = 1 (see Figure 19) - the last descriptor had NO = 0 (maskable by TE in the channel spec.) FO: issued if the MUNICH32X was unable to access the shared memory in time either for new data to be sent or for a new descriptor. (maskable by TE in the channel spec.)
Data Sheet
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Detailed Protocol Description Example V.110/X.30 channel with CS = 0 (required) INV = 0 CRC = 0 TRV variable (all values shown in examples) FA = 0 (required) MODE = 10 (V.110/X.30) Little Endian Data Format Channel No. 1F
Generate HI-Interrupt 2000101F
Generate HI-Interrupt 2000101F
31 00028000
0
31 20030000
0
31 20018000
0
31 00030000
0
0
0
0
0
E, S, X
31 0 1 75 40 00 00
31 0 DATA 1 XX FA D6 C3 E, S, X
31 0 2 8A 80 00 00
31 0 DATA 2 XX D1 E2 C0
ITD10442
Figure 49
Example of V.110/X.30 Transmit Mode
Note: The first transmit descriptor must have the V.110-bit set.
Data Sheet
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Detailed Protocol Description TRV = 00
0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 0 1 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 SA X SB 1 E1E2E3E4E5E6E7
D6 = 11 0 1 0 1 1 0 B6B5B4B3B2B1
FA = 11 1 1 1 0 1 0 B6B5B4B3B2B1
Change of E-, S-, X-bits
Data Sheet
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Detailed Protocol Description TRV = 01
0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 SA X SB 1 E1E2E3E4E5E6E7
FA (last byte of DATA 1)
11 1 1 1 0 1 0 B6B5B4B3B2B1
C0 (first byte of DATA 2) Change of E-, S-, X-bits E2 = 1 1 1 0 0 0 1 0 B6B5B4B3B2B1
11 0 0 0 0 0 0 B6B5B4B3B2B1
D1 = 1 1 0 1 0 0 0 1 B6B5B4B3B2B1
TRV = 10
0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 SA X SB 1 E1E2E3E4E5E6E7
Change of E-, S-, X-bits E2 = 1 1 1 0 0 0 1 0 B6B5B4B3B2B1 D1 = 1 1 0 1 0 0 0 1 B6B5B4B3B2B1
Data Sheet
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Detailed Protocol Description TRV = 11
0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 1 Change of E-, S-, X-bits
For INV = 1 (channel inversion) all bits are inverted. In big endian mode the data sections must have the following form to yield the same output data:
31 0 E, S, X 1 00 00 40 75
31 0 DATA 1 C3 86 FA XX
31 0 31 0 E, S, X 2 00 00 80 8A DATA 2 C0 E2 D1 XX XX XX 00 03
ITD05038
Data Sheet
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Detailed Protocol Description Receive Direction General Features In receive direction - the starting sequence (00H followed by a `1'-bit) after initialization of loss of synchronism is detected. - the synchronization pattern is monitored, after 3 consecutive erroneous frames a loss of synchronism is detected. - a change of E-, S-, X-bits is monitored and reported by an interrupt. - the data bits are extracted and written into the data section. More detailed description of the individual features: The receiver can be in two different states:
RESET
Unsynchronous State 8 * "0" bit followed by a "1" bit Synchronous State
ITD05039
3 Consecutive Erroneous Frames (with a Frame Error)
Figure 50
Receiver States in V.110/X.30
1. Data extraction and monitoring of a change of E-, S-, X-bits and synchronization pattern is only performed in synchronized state. 2. In the unsynchronized state the receiver waits for the synchronization pattern. The `1'bit is then interpreted as bit 1 of octet 2. 3. During the synchronized state a change of E, S, X-bits from one frame to the next and even within a frame (for SA, SB bits) is monitored. Only one interrupt per frame is reported even if SA e.g. changes 3 times within the frame. The E-, S-, X-bits reported in the interrupt are S9 for SB and S8 for SA and the second occurrence of X for X. 4. The bits written into the data section are marked by O in Table 8 to Table 10. As shown, bits repeated in the serial data are only strobed at their last instance.
Data Sheet
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Detailed Protocol Description Table 8 Framing for Networks with 600-bit/s Data Rate Intermediate Rate = 8 Kbit/s, i.e. Subchannelling with Only 1 Fill/ Mask Bit Set 1 0 1 1 1 1 1 1 1 1 1 2 0 B1 B1 B2 B3 E1 B4 B4 B5 B6 3 0 B1 B1 B2 B3 E2 B4 B4 B5 B6 4 0 B1 B2 B2 B3 E3 B4 B5 B5 B6 5 0 B1 B2 B2 B3 E4 B4 B5 B5 B6 6 0 B1 B2 B3 B3 E5 B4 B5 B6 B6 7 0 B1 B2 B3 B3 E6 B4 B5 B6 B6 8 0 S1 X S3 S4 E7 S6 X S8 S9
Octet No. 1 2 3 4 5 6 7 8 9 10
Table 9
Framing for Networks with 1200-bit/s Data Rate Intermediate Rate = 8 Kbit/s, i.e. Subchannelling with Only 1 Fill/ Mask Bit Set 1 0 1 1 1 1 1 1 1 1 1 2 0 B1 B2 B4 B5 E1 B7 B8 B10 B11 3 0 B1 B2 B4 B5 E2 B7 B8 B10 B11 4 0 B1 B3 B4 B6 E3 B7 B9 B10 B12 5 0 B1 B3 B4 B6 E4 B7 B9 B10 B12 6 0 B2 B3 B5 B6 E5 B8 B9 B11 B12 7 0 B2 B3 B5 B6 E6 B8 B9 B11 B12 8 0 S1 X S3 S4 E7 S6 X S8 S9
Octet No. 1 2 3 4 5 6 7 8 9 10
Data Sheet
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Detailed Protocol Description Table 10 Framing for Networks with 2400-bit/s Data Rate Intermediate Rate = 8 Kbit/s, i.e. Subchannelling with Only 1 Fill/ Mask Bit Set 1 0 1 1 1 1 1 1 1 1 1 2 0 B1 B4 B7 B10 E1 B13 B16 B19 B22 3 0 B1 B4 B7 B10 E2 B13 B16 B19 B22 4 0 B2 B5 B8 B11 E3 B14 B17 B20 B23 5 0 B2 B5 B8 B11 E4 B14 B17 B20 B23 6 0 B3 B6 B9 B12 E5 B15 B18 B21 B24 7 0 B3 B6 B9 B12 E6 B15 B18 B21 B24 8 0 S1 X S3 S4 E7 S6 X S8 S9
Octet No. 1 2 3 4 5 6 7 8 9 10
Table 11
Framing for Networks with 4800-, 9600-, 19200-, 38400-bit/s Data Rate Intermediate Rate = 8, 16, 32, 64 Kbit/s, i.e. Subchannelling with 1, 2, 4, 8 Fill/Mask Bit Set 1 0 1 1 1 1 1 1 1 1 1 2 0 B1 B7 B13 B19 E1 B25 B31 B37 B43 3 0 B2 B8 B14 B20 E2 B25 B32 B36 B44 4 0 B3 B9 B15 B21 E3 B27 B33 B39 B45 5 0 B4 B10 B16 B22 E4 B29 B35 B41 B47 6 0 B5 B11 B17 B23 E5 B29 B35 B41 B47 7 0 B6 B12 B18 B24 E6 B30 B36 B42 B48 8 0 S1 X S3 S4 E7 S6 X S8 S9
Octet No. 1 2 3 4 5 6 7 8 9 10
Data Sheet
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Detailed Protocol Description They are grouped together in the form:
31 0 1 1 B6 B5 B4 B3 B2 B1 1 1 B12 B11 B10 B9 B8 B7 1 1 B18 B17 B16 B15 B14 B13 1 1 B24 B23 B22 B21 B20 B19
(in big endian mode)
31 0 1 1 B24 B23 B22 B21 B20 B19 1 1 B18 B17 B16 B15 B14 B13 1 1 B12 B11 B10 B9 B8 B7 1 1 B6 B5 B4 B3 B2 B1
(in little endian mode) where for the 600 bit/s e.g. B1 to B6 belong to the first 10-octet frame, B7 to B12 belong to the second 10-octet frame etc.
Data Sheet
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Detailed Protocol Description Options The different options for this mode are the framing pattern as shown in Table 8 to Table 11. They are programmed by the bits TRV (Transmission Rate) in the Channel Specification. Interrupts The possible interrupts for this mode are FRC: issued if the receiver has detected a change of S-, X-, E-bits; the value of the bits E7, ..., E1, S8 for SA and S9 for SB and the second occurrence of X within the 10octet frame is reported within the same interrupt. (maskable by CH in the channel specification) HI: issued if the HI bit is detected in the transmit descriptor (not maskable). ERR: issued if one of the following receive errors has occurred: - a fast receive abort channel command was issued (this leads to a setting of the RA bit in the status byte) - data could only partly be stored due to internal buffer overflow of RB - 3 consecutive frames had an error in the synchronization pattern (loss of synchronism) - the HOLD bit in the receive descriptor was detected (this leads to a setting of the RA bit in status in the receive descriptor). (maskable by RE in the channel specification) FO: issued if due to inaccessibility of the internal buffer (RB) one or more changes of E-, S-, X-bits and/or loss of synchronism information have been lost. (maskable by RE in the channel specification)
Example V.110/X.30 channel with CS = 0 (required) INV = 0 CRC = 0 TRV = 00 (600 bit/s) FA = 0 MODE = 10 (V.110/X.30) Big Endian Data Format Channel No. D
Data Sheet
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Detailed Protocol Description
... 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0
MUNICH32X waits for synchronization after reset
1 1 1 0 1 0 0 1 E9 H B6 B5 B4 B3 B2 B1
Reported as X Reported as SA Reported as SB Error in synchronization pattern
1 1 0 0 1 0 1 0 CAH B6 B5 B4 B3 B2 B1
No change of E, S, X Bits
Change of E, S, X Bits; but SA is still reported as '1'
1 1 1 1 1 0 1 0 FA H B6 B5 B4 B3 B2 B1
Reported as SA Error in synchronization pattern
1 1 0 1 0 0 1 0 D2 H B6 B5 B4 B3 B2 B1 No change of E, S, X Bits Error in synchronization pattern
ITD10443
Figure 51
Example of V.110/X.30 Receive Mode
Data Sheet
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Detailed Protocol Description
0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
EDH No change of E, S, X Bits
Error in synchronization pattern
FF H
Change of E, S, X Bits
FF H Change of E, S, X Bits
No error in synchronization pattern
C0 H Change of E, S, X Bits
Error in synchronization pattern
ITS08220
Figure 52
Example of V.110/X.30 Receive Mode
Data Sheet
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Detailed Protocol Description
30CB600D 30CB600D 3000010D 1 Desc 31 00080000 0
st
30FFE00D 20EAE00D 3080000D 3000100D 2 31
nd
Desc 0
20040000
40042000 31 0 E9 CA FA D2
40040000 31 0 ED FF FF C0
ITD10444
Loss of Synch.
Figure 53
Loss of Synchronism in V.110/X.30
In little endian mode, the data sections have the form:
of 1st Desc 31 0 D2 FA CA E9
of 2 nd Desc 31 0 C0 FF FF ED
ITD05041
Data Sheet
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Microprocessor Bus Interface
5
Microprocessor Bus Interface
The MUNICH32X may be configured either for 33 MHz/32-bit PCI operation, or for a 33 MHz/32-bit De-multiplexed bus. The MUNICH32X's DEMUX input pin is used to select the desired configuration (`0' = PCI, `1' = DEMUX). The MUNICH32X provides identical DMA controller capability for both interfaces. When in the PCI configuration, connection to other peripherals (e.g., ISDN transceivers, FALC54, ISAC-S or ESCC2) may be made through the MUNICH32X's Local Bus Interface (LBI).
5.1
PCI Bus Interface
In this configuration, the MUNICH32X interfaces directly to a 33 MHz/32-bit PCI bus. During run-time, the MUNICH32X operates mostly as a PCI Master; it may be accessed by the host processor as a PCI Slave. During device configuration, the MUNICH32X operates only as a slave device; memory transactions are used to configure the device. The MUNICH32X is compliant with the PCI specification 2.1 at up to 33 MHz. In addition, the MUNICH32X supports little/big endian byte swapping for the data section, and unaligned-byte accesses for transmit data.
5.1.1
PCI Transactions Supported
Memory accesses as a PCI Master: The MUNICH32X supports both the PCI Memory Write and PCI Memory Read commands. For the PCI Memory Write command, it writes to an agent mapped in the memory access space, while for the PCI Read command, it reads from an agent mapped in the memory address space. I/O accesses as a PCI Master: The MUNICH32X does not support the PCI I/O Write nor PCI I/O Read commands. Memory accesses as a PCI Slave: The MUNICH32X supports both the PCI Memory Write and PCI Memory Read commands. For the PCI Memory Write command, the MUNICH32X is written to as an agent mapped in the memory address space, while for the PCI Memory Read command, the MUNICH32X is read from as an agent mapped in the memory address space. I/O accesses as a PCI Slave: The MUNICH32X does not support the PCI I/O Write nor PCI I/O Read commands. Burst Capability: Read/write descriptors: up to 3 DWORDs, read/write data for MUNICH32 core: 1 DWORD, read/write data for LBI interface: up to 8 DWORDs.
5.1.2
PCI Configuration Space Registers
The PCI Configuration Space Registers of the MUNICH32X are listed Table 12.
Data Sheet
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Microprocessor Bus Interface For a detailed description of the standard registers refer to Chapter 6 (Configuration Space) of the PCI specification 2.1. Table 12 PCI Configuration Space Registers Read/ Write Absolute Address Pins IDSEL & AD(7:2) 00H 04H 08H 0CH Reset Value
Register Name
Standard Configuration Space Registers Device ID/Vendor ID Status/Command Class Code/Revision ID V2.2 Builtin Self Test/Header Type/ Latency Timer/ Cache Line Size Base Address 1 Base Address 2 Base Address 3 Base Address not used Cardbus CIS Pointer Subsystem ID/ Subsystem Vendor ID Expansion ROM Base Address Reserved Reserved Maximum Latency/ Minimum Grant/ Interrupt Pin/ Interrupt Line Reserved Reserved Reserved PCI Configuration Space Reset DID/VID STA/CMD CC/RID R R/W R 2101110AH 02800000H 02800013H 00000000H
BIST/HEAD/ R/W LATIM/ CLSIZ BAR1 BAR2 BAR3 BARX CISP R/W R/W R/W R/W R
10H 14H 18H 1CH-24H 28H 2CH 30H 34H 38H 3CH
00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 10020100H
SSID/SSVID R ERBAD RES34 RES38 MAXLAT/ MINGNT/ INTPIN/ INTLIN RES40 RES44 RES48 PCIRES R/W R/W R/W R/W
User Defined Configuration Space Registers R/W R/W R/W R/W 40H 44H 48H 4CH 00000000H 00000000H 00000000H 00000000H
Data Sheet
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Microprocessor Bus Interface The only non-standard PCI Configuration Space register is PCIRES, as described below.
5.1.3
PCI Configuration Space - Detailed Register Description
Status/Command register description. Offset address: 04H
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Status DPE SSE RMA RTA 0 0 0 DPED 1 0 0 0 0 0 0 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Command 0 0 0 0 0 0 FBBE SERRE 0 PER 0 0 SC BM MS IOS
Status and Command register bits Bit Location 31 Symbol DPE Description Detected Parity Error This bit is set by the device whenever it detects a parity error, even if parity error handling is disabled (as controlled by bit 6 in the Command register).
Data Sheet
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Microprocessor Bus Interface Status and Command register bits 30 SSE Signaled System Error This bit will be set when * the SERR Enable bit is set in the Command register and one of the following events occured: 1. A transaction in which the MUNICH32X acted as a master is terminated with master abort. 2. A transaction in which the MUNICH32X acted as a master is terminated with target abort by the involved target. 3. The transaction has an address parity error and the Parity Error Response bit is set. 29 RMA Received Master Abort This bit is set whenever the MUNICH32X aborts a transaction with master abort. This occurs when no device responds. Note: In version 1.1 of the MUNICH32X the device does not properly abort the transaction. Received Target Abort This bit is set whenever a device responds to a master transaction of the MUNICH32X with a target abort. Note: In version 1.1 of the MUNICH32X the device does not properly abort the transaction. Signaled Target Abort The MUNICH32X will never signal "Target Abort". DEVSEL Timing The MUNICH32X is a medium device. Data Parity Error Detected This bit is set when the following three conditions are met: 1. the device asserted PERR itself or observed PERR asserted 2. the device setting the bit acted as the bus master for the transaction in which the error occurred 3. and the Parity Error Response bit is set in the Command register Fast Back-to-Back Capable The MUNICH32X is fast Back-to-Back capable. UDF Supported No UDFs are supported by the MUNICH32X
28
RTA
27 26, 25 24
0B 01B DPED
23 22
1B 0B
Data Sheet
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Microprocessor Bus Interface Status and Command register bits 21 20 ... 16 15 ... 10 9 0B 00000B 000000B FBBE 66 MHz Capable The MUNICH32X is not 66 MHz capable Reserved Reserved Fast Back-to-Back enable A value of `1' means the MUNICH32X is allowed to generate fast Back-to-Back transactions to different agents. A value of `0' means the MUNICH32X is only allowed to generate fast Back-to-Back transaction to the same agent. SERR Enable A value of `1' enables the SERR driver. A value of `0' disables the SERR driver. Wait Cycle Control The MUNICH32X does never perform address/data stepping. Parity Error Response When this bit is set the MUNICH32X will take its normal action when a parity error is detected. When this bit is `0' the MUNICH32X ignores any parity errors that it detects and continues normal operation. VGA Palette Snoop The MUNICH32X is no VGA-Device. Memory Write and Invalidate Enable The "Invalidate" command is not supported by the MUNICH32X. Special Cycles All special cycles are ignored. Note: Although this bit can be set it has no effect. Bus Master A value of `1' enables the bus master capability. Note: Before giving the first action request it is necessary to set this bit. Memory Space A value of `1' allows the MUNICH32X to respond to Memory Space Addresses. Note: This bit must be set before the first read/write transactions to the MUNICH32X will be started.
8
SERRE
7 6
0B PER
5 4
0B 0B
3
SC
2
BM
1
MS
Data Sheet
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Microprocessor Bus Interface Status and Command register bits 0 IOS IO Space I/O Space accesses to the MUNICH32X are not supported. Note: Although this bit can be set it has no effect.
Data Sheet
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Microprocessor Bus Interface PCI Configuration Space Reset Register Access Offset Address Reset Value : read/write : 4CH : 00000000H
31 PCIRES 0 15 PCIRES RST0 0000H Serial PCM Core Reset 0 0 0 0 0 0 0 0 0 0 0 RST(2:0)
16 0 0
Setting this bit to `1' has the same effect for the Serial PCM core as an external RST; i.e., the PCM core is forced to go into standby mode. Programming this bit to `0' in turn corresponds to deasserting RST (refer to Chapter 10.1). RST1 LBI Reset Setting this bit to `1' has the same effect for the LBI functional blocks, as an external RST; i.e., the LBI EBC/DMSM/Mailbox modules are forced to go into reset mode and the DMAC is forced to go into standby mode. Programming this bit to `0' in turn corresponds to deasserting RST (refer to Chapter 10.1). RST2 SSC/IOM(R)-2 Reset Setting this bit to `1' has the same effect for the SSC and IOM(R)-2 functions as an external RST; i.e., both are forced to go into standby mode. Programming this bit to `0' in turn corresponds to deasserting RST (refer to Chapter 10.1).
Data Sheet
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Microprocessor Bus Interface
5.2
De-multiplexed Bus Interface
The MUNICH32X may be configured for a 33 MHz/32-bit De-multiplexed bus for connection to systems with de-multiplexed processors such as the i960Hx or MC68EC0x0. The DEMUX input pin is used to select the desired configuration (`0' = PCI, `1' = De-multiplexed mode). The De-multiplexed bus interface is a synchronous interface very similar to the PCI bus with the following exceptions: 1. The W/R input/output signal replaces the function of the PCI command nibble of the C/BE(3:0) bit field. 2. Note that in De-multiplexed mode, as in PCI mode, the MUNICH32X provides only the first address of a Master burst read or write transaction. Table 13 Pins dedicated Non-PCI Pins in the De-multiplexed Bus Configuration Symbol DEMUX Input (I) Function Output (O) I I/O I/O De-multiplexed Bus Enable `0' = PCI, `1' = DEMUX Address Bus Write/Read
LBI address A(31:2) & data dedicated W/R
In this mode, 4-DWORD Master Read and Write Burst capability may be enabled via the DBE bit field in the Configuration register CONF; this bit is valid only if DEMUX = `1'. Burst Capability: DBE = 0: No burst capability, all transactions are 1 DWORD transfers. DBE = 1: Burst capability up to 4 DWORDs, currently supported: read/write descriptors: up to 3 DWORDs, read/write data for MUNICH32 core: 1 DWORD Even when burst capability has been selected, the target can request the MUNICH32X to stop the current transaction by asserting the STOP signal. The following diagrams illustrate the timing waveforms for both single and burst transactions.
Data Sheet
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Microprocessor Bus Interface
0ns CLK FRAME D(31:0) A(31:2) BE(3:0) W/R TRDY Address don t care Address BE(3:0) READ Access Data
100ns
200ns
Address don t care Address BE(3:0) WRITE Access
Data
ITD10344
Figure 54
Master Single READ Transaction followed by a Master Single WRITE Transaction in De-multiplexed Bus Configuration
0ns CLK FRAME D(31:0) A(31:2) BE(3:0) W/R TRDY BE(3:0) Address don t care Data 1
100ns
200ns
Data 2
Data 3
Data 4
Address BE(3:0) BE(3:0) BE(3:0)
WRITE / READ Access
ITD10345
Figure 55
Master Burst WRITE/READ Access in De-multiplexed Bus Configuration
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Microprocessor Bus Interface When in De-multiplexed configuration, the MUNICH32X adheres to the PCI bus protocol and timing specification, except for the address and command handling. In this mode, the addresses are provided on a separate address bus A(31:2) to eliminate the need for external de-multiplexing buffers. The address lines A(31:2) correspond to the address lines AD(31:2). The address becomes valid with the falling edge of FRAME and stays valid for the standard PCI address phase, the turn-around cycle and the entire data phase. The burst order, normally coded in AD(1:0), is not supported in De-multiplexed PCI mode. In burst mode the addresses have to be incremented externally for each single transfer. Moreover, in De-multiplexed PCI mode the command signals are not used. Instead of the command signals a separate pin W/R (I/O) provides the Write/Read strobe signal. The Write/Read becomes valid with the falling edge of FRAME and stays valid for the standard PCI address phase, the turn-around cycle and the entire data phase. The following four commands are supported: Table 14 W/R 0 1 0 1 Supported Commands in De-multiplexed Mode IDSEL 0 0 1 1 Master Mode memory read memory write not supported not supported Slave Mode MUNICH32X register read MUNICH32X register write MUNICH32X PCI Configuration read MUNICH32X PCI Configuration write
Note: When designing a de-multiplexed system with the MUNICH32X in De-multiplexed Bus mode it is the responsibility of the glue logic to meet the bus timing/protocol of the PCI specification and of the memory devices that are used in the system. When the MUNICH32X operates in master mode, the bus cycle, for example, can be delayed by the TRDY signal.
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Local Bus Interface (LBI)
6
6.1
Local Bus Interface (LBI)
Overview
The MUNICH32X provides capability for the PCI host system to access LBI peripherals, as well as capability for an intelligent LBI peripheral (e.g., a CPU) to access the PCI host system.
.
PCI Bus
32
Tx DMAC
Rx DMAC
TFIFO
RFIFO
LBI
Data Mode State Machine (DMSM)
Direct Access
External Bus Controller (EBC) Control 16 Bus 16 Data Bus Address Bus
ITD10346
16
Local Bus
Figure 56
Local Bus Interface Block Structure
Note that the LBI is only available when the MUNICH32X is configured for the PCI mode. When in de-multiplexed mode, the LBI address and data pins interface to the system address bus. Table 15 LBI Peripheral Transaction Options Write PCI posted operation via Mailbox registers Slave Slave PCI Retry operation via Mailbox registers
Peripheral Type PCI Transaction Read Non-Intelligent Intelligent
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Local Bus Interface (LBI)
6.1.1
Transactions with Non-intelligent Peripherals
Standard PCI Slave transactions are used when the PCI host system communicates with non-intelligent LBI peripherals. The MUNICH32X handles 8-, 16- or 32-bit PCI transactions and translates them into the corresponding local bus transactions, e.g. a 32bit PCI transaction results in two 16-bit local bus transactions when the local bus interface is configured for 16-bit operations. For reads, a PCI Retry sequence of operations is performed, in which the MUNICH32X will immediately terminate the PCI transaction (and request a retry) until it terminates the transaction to the LBI. The MUNICH32X uses the retry procedure because the time to complete the data phase will require more than the maximum allowed 16 PCI clocks (from the assertion of FRAME to the completion of the first data phase). Data transfer will be successfully completed within a PCI retry cycle. The number of necessary PCI retry cycles depend on PCI arbitration behavior and the time it needs to terminate the transaction on the local bus; PCI TRDY wait states will not be added for the sequential retry read cycles unless the LBI arbitration time is excessive. For write transactions, the MUNICH32X will store a single data DWORD and then immediately terminate the PCI transaction successfully. It will then arbitrate the local bus and perform the write transaction after being granted depending on the selected number of wait states and LRDY bus control signal. Thus write accesses to LBI are performed as `posted write' transactions from the PCI view. A consecutive write transaction results in PCI retry cycles in the case that the preceding write transaction is not yet finished on LBI. Note that the MUNICH32X performs single word PCI Slave read or write transactions only; Slave burst transactions to LBI are not supported.
6.1.2
Transactions with Intelligent Peripherals
The MUNICH32X uses an `exclusive-access' Mailbox Command Register MBCMD to control the transfer of information between the PCI host system and an intelligent LBI peripheral (e.g., a CPU). The PCI host system always reads the contents that was written to Mailbox Command Register by the LBI peripheral, while the intelligent LBI peripheral always reads the contents that was written to Mailbox Command Register by the PCI host system. As an example, consider when the PCI host system wants to transfer data to an intelligent LBI peripheral. First, assuming it has `ownership' of the Mailbox registers, it loads data into the Mailbox Data Registers, and then writes a `1' to INPCI bit field of the Mailbox Command Register. This last action causes the LINTO output signal to become asserted, indicating to the intelligent LBI peripheral that data is ready. The intelligent LBI peripheral will read Mailbox Command Register (which deasserts the LINTO output signal and resets the INPCI bit field of Mailbox Command Register), and then reads the data from the Mailbox Data Registers. Finally, it writes a `1' to the INLBI
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Local Bus Interface (LBI) bit field of Mailbox Command Register, which causes an interrupt to be generated to the PCI host system, informing the PCI host system that the data transfer is complete. The PCI host system completes its participation of the transaction by reading the Status Register STAT (to determine the cause of the interrupt), writing a `1' to the Status Acknowledge Register's MBI bit field to deassert the PCI INTA signal. Alternately, consider when the intelligent LBI peripheral wants to transfer data to the PCI host system. First, assuming it has `ownership' of the Mailbox registers, it loads data into the Mailbox Data Registers, and then writes a `1' to the INLBI bit field of Mailbox Command Register. This causes an interrupt to be generated to the PCI host system, indicating to the PCI host system that data is ready. The PCI host system reads the Status Register STAT (to determine the cause of the interrupt), writes a `1' to the Status Acknowledge Register's MBI bit field to deassert the PCI INTA signal, and then reads the data from the Mailbox Data Registers. Next, it writes a `1' to the INPCI bit field of the Mailbox Command Register, which asserts the LINTO signal to the LBI peripheral. The intelligent LBI peripheral completes its participation of the transaction when it reads Mailbox Command Register, which deasserts the LINTO signal and resets the INLBI bit field of the Mailbox Command Register.
6.1.3
Software Arbiter/Data Transfer Control
The architecture of the Mailbox registers requires the PCI host system software to provide Mailbox arbitration. The primary data transfer control requirement is that only the current `owner' of the Mailbox registers may write data into the Mailbox Data Registers. Typically, upon exiting reset, the PCI host system becomes the Mailbox `owner' and may transfer data to the LBI. If the LBI desires to transfer data to the PCI host system, it must generate an interrupt to the PCI host system (by writing a `1' to INLBI bit field in Mailbox Command Register MBCMD), informing the PCI host system that it requests `ownership' of the Mailbox registers. It is the responsibility of the PCI host system software arbiter to handle the request/grant protocol.
6.1.4
Mailbox Registers
The organization of the Mailbox registers is partioned into an `exclusive-access' Mailbox Command Register, and into seven Mailbox Data Registers, as shown below.
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Local Bus Interface (LBI)
15 FC F8 F4 F0 EC E8 E4
Access from PCI host interface 87 Mailbox Data Register 7 Mailbox Data Register 6 Mailbox Data Register 5 Mailbox Data Register 4 Mailbox Data Register 3 Mailbox Data Register 2 Mailbox Data Register 1
0 7 6 5 4 3 2 1
15
Access from LBI peripheral 87 Mailbox Data Register 7 Mailbox Data Register 6 Mailbox Data Register 5 Mailbox Data Register 4 Mailbox Data Register 3 Mailbox Data Register 2 Mailbox Data Register 1 INLBI
0
E0 Mailbox Command Register INPCI
0 Mailbox Command Register
ITD10347
Figure 57
LBI Mailbox Structure
Note: The Mailbox registers should only be used for communication between the PCI host system and an intelligent LBI peripheral. The Mailbox Command Register provides the PCI/LBI Mailbox registers exclusive access bit INPCI/INLBI and 15 bits for user defined interrupt information (refer to Section 11.2.7). It may for example perform the following functions: * * * * interrupt generation, deassertion of the LINTO interrupt signal by the intelligent LBI peripheral, end-of-data-transfer indication, and end-of-transaction indication.
Note that an intelligent LBI peripheral will deassert the LINTO interrupt signal by reading Mailbox Command Register MBCMD, while the PCI host system will deassert the PCI INTA interrupt signal by writing a `1' to the MBI bit field in Status Acknowledge Register STACK. When a mailbox interrupt from LBI peripheral is detected, the LBI Mailbox Interrupt Vector is generated and written to the host memory address specified in Peripheral Interrupt Queue Base Address (PIQBA) register. Note that an interrupt vector is generated after a write access to bit field INPCI/ INLBI of MBCMD, even when this bit has not been reset between two write accesses. The structure of the LBI Mailbox interrupt vector is as follows:
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Local Bus Interface (LBI) LBI Mailbox Interrupt Vector 31 MB_IV 1 15 MB_IV IV Interrupt Vector Contains the values of Mailbox Command Register's bit fields MBINT(15:1). LBI Block Overview Additionally to the Mailbox registers, the Local Bus Interface consists of three main functional blocks (refer to Figure 56): * the External Bus Controller (EBC), * the Data Mode State Machine (DMSM), and * the DMA Controllers (DMAC). They are described in detail in the following chapters. IV(15:1) 0 1 1 0 0 0 0 00H 0 1 16
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Local Bus Interface (LBI)
6.2
LBI External Bus Controller (EBC)
The External Bus Controller (EBC) provides a flexible bus interface to connect a wide range of peripherals. In normal mode, this interface is master and drives peripheral devices. It provides the ability to select busses of different configuration: 8 bit multiplexed/de-multiplexed or 16 bit multiplexed/de-multiplexed. The configurable pins of DMA support/General Purpose Bus provide alternate functionality to support the LBI pins. The EBC performs `funneling' of data to or from the LBI FIFOs (as DWORDs) to the 8-/ 16-bit LBI bus. The EBC also supports bus arbitration. It inter-works with all other blocks of the LBI (FIFOs, DMSM and Mailbox registers), as well as supporting a `Direct Access' path to the internal bus. It also provides the de-multiplexed address lines on the LBI address pins, if the MUNICH32X is operated in de-multiplexed mode. The function of the EBC is controlled via the LBI Configuration register LCONF. It specifies the external bus cycles in terms of address (multiplexed/de-multiplexed), data (16-bit/8-bit) and control signal length (wait states).
6.2.1
External Bus Modes
Multiplexed Bus Modes In the 16-bit multiplexed bus mode both the address and data lines use the pins LD(15:0). The address is time-multiplexed with the data and has to be latched externally. The width of the required latch depends on the selected data bus width, i.e. an 8-bit data bus requires a byte latch (the address bits LD15 ... LD8 on the LBI port do not change, while on LD7 ... LD0 address and data are multiplexed), a 16-bit data bus requires a word latch (the least significant address line LA0 is not relevant for word accesses). In de-multiplexed mode, the address lines are permanently output on pins LA(15:0) and do not require latches. The EBC initiates an external access by generating the Address Latch Enable signal (LALE) and then placing an address on the bus. The falling edge of LALE triggers an external latch to capture the address. After a period of time during which the address must have been latched externally, the address is removed from the bus. The EBC now activates the respective command signal (LRD, LWR, LBHE). Data is driven onto the bus either by the EBC (for write cycles) or by the external memory/peripheral (for read cycles). After a period of time, which is determined by the access time of the memory/ peripheral, data become valid. Read cycles: Input data is latched and the command signal is now deactivated. This causes the accessed device to remove its data from the bus which is then tri-stated again. Write cycles: The command signal is now deactivated. The data remain valid on the bus until the next external bus cycle is started.
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Local Bus Interface (LBI)
Extended ALE LALE Data In LRD Data Out LWR
ITD10348
Address
Data
Address
Data
Figure 58
Multiplexed Bus Cycle
Demultiplexed Bus Modes The de-multiplexed bus modes use the LBI port pins LA(15:0) for the 16-bit address and the LBI port pins LD(15:0) for 8/16-bit data. The EBC initiates an external access by placing an address on the address bus. The EBC then activates the respective command signal (LRD, LWR, LBHE). Data is driven onto the data bus either by the EBC (for write cycles) or by the external memory/peripheral (for read cycles). After a period of time, which is determined by the access time of the memory/peripheral, data become valid. Read Cycles: Input data is latched and the command signal is now deactivated. This causes the accessed device to remove its data from the data bus which is then tri-stated again. Write Cycles: The command signal is now deactivated. If a subsequent external bus cycle is required, the EBC places the respective address on the address bus. The data remain valid on the bus until the next external bus cycle is started.
Data Sheet
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Local Bus Interface (LBI)
Address Data In LRD Data Out LWR
ITD10349
Figure 59
Demultiplexed Bus Cycle
External Data Bus Width The EBC can operate on 8-bit or 16-bit wide external memory/peripherals. A 16-bit data bus uses the LBI port pins LD(15:0), while an 8-bit data bus only uses LD(7:0). This saves bus transceivers, bus routing and memory cost at the expense of transfer time. The EBC can control byte accesses on a 16-bit data bus. Byte accesses on a 16-bit data bus require that the upper and lower half of the memory can be accessed individually. In this case the upper byte is selected with the LBHE signal, while the lower byte is selected with the AD0 signal. The two bytes of the memory can therefore be enabled independently from each other (or together when accessing words). Devices such as the ESCC2 also provide a BHE input and hence allow byte accesses in 16-bit bus mode. When reading bytes from an external 16-bit device, 16-bit words may be read and the EBC automatically selects the byte to be input and discards the other. However, care must be taken when reading devices that change their state when being read, like FIFOs, interrupt status registers, etc. In this case individual bytes should be selected using BHE and A0.
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Local Bus Interface (LBI) Switching between the Bus Modes The EBC bus type can be switched dynamically by software. However, the user needs to keep track of the peripheral that is being addressed (multiplexed mode or demultiplexed mode) with the selected bus type. Master/Slave bus mode is also configured/arbitrated dynamically by the device itself.
6.2.2
Programmable Bus Characteristics
Important timing characteristics of the external bus interface are user programmable to adapt it to a wide range of different external bus and memory configurations with different types of memories and/or peripherals. The following parameters of an external bus cycle are programmable: * Memory Cycle Time (extendable with 1 ... 15 wait states) defines the allowable access time. * READY Control defines, if a bus cycle is terminated internally or externally. Programmable Memory Cycle Time The user can adjust the EBC external bus cycles to the access time of the respective memory or peripheral. This access time is the total time required to move the data to the destination. It represents the period of time during which the EBC's signals do not change.
LALE Data In LRD Data Out LWR MCTC wait states (1...15) Address Data Address Data
ITD10350
Figure 60
Memory Cycle Time
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Local Bus Interface (LBI) The external bus cycles of the EBC can be extended for a memory or peripheral, which cannot keep pace with the EBC's maximum speed, by introducing wait states during the access (see figure above). The memory cycle time wait states can be programmed in increments of one EBC system clock (LCLKOUT) within a range from 0 ... 15 (default after reset) via the MCTC bit fields of the LBI Configuration register LCONF. A number of (15 - ) wait states will be inserted.
6.2.3
LRDY Controlled Bus Cycles
For situations, where the programmable wait states are not sufficient, or where the response (access) time of a peripheral is not constant, the MUNICH32X EBC interface provides external bus cycles that are terminated via a LRDY input signal. In this case the EBC first inserts a programmable number of waitstates (0 ... 7) and then monitors the LRDY line to determine the actual end of the current bus cycle. The external device drives LRDY low in order to indicate that data either have been latched (write cycle) or are available (read cycle).
LALE LRD / LWR 1.WS LRDY Data Out
ITD10351
Figure 61
LRDY Controlled Bus Cycles
The LRDY function is enabled via the RDEN bit fields in the LBI Configuration register. When this function is selected (RDEN = `1'), only the lower 3 bits of the respective MCTC bit field define the number of inserted waitstates (0 ... 7), while the MSB of bit field MCTC selects the LRDY operation.
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Local Bus Interface (LBI) The LRDY signal is always synchronized at the input port pin. An asynchronous LRDY signal that has been activated by an external device may be deactivated in response to the trailing (rising) edge of the respective command (LRD or LWR). Combining the LRDY function with predefined waitstates is advantageous in two cases. Memory components with a fixed access time and peripherals operating with LRDY may be grouped into the same address window. The (external) wait states control logic in this case would activate LRDY either upon the memory's chip select or with the peripheral's LRDY output. After the predefined number of wait states the EBC will check its LRDY line to determine the end of the bus cycle. For a memory access it will be low already, for a peripheral access it may be delayed. As memories tend to be faster than peripherals, there should be no impact on system performance. When using the LRDY function with `normally-ready' peripherals, it may lead to erroneous bus cycles, if the LRDY line is sampled too early. These peripherals pull their LRDY output low, while they are idle. When they are accessed, they deactivate LRDY until the bus cycle is complete, then drive it low again. By inserting predefined wait states, the first LRDY sample point can be shifted to a time by that the peripheral has safely controlled the LRDY line (e.g., after 2 wait states in the figure above).
6.2.4
Configuring the External Bus Controller
The properties of a bus cycle usage of LRDY, external bus mode and wait states are controlled by LBI Configuration register LCONF. This allows the use of memory components or peripherals with different interfaces within the same system, while optimizing accesses to each of them. The current interupt signal and bus arbitration status of the EBC is indicated by the LBI Status Register LSTAT: * LSTAT.HLD indicates the hold mode of the EBC. * LSTAT.INT1 indicates an interrupt on LINT1. * LSTAT.INT2 indicates an interrupt on LINT2. The reset control of the EBC is handled by the LBI Configuration Register: * LCONF.EBCRES resets the EBC in an initial state (same as hardware reset state). For normal EBC operation bit LCONF.EBCRES must be set to `1' again.
6.2.5
EBC Idle State
Upon reset, the LBI is in bus slave mode with control strobes as inputs. The EBC can then be programmed to be master or slave by software. When the EBC bus interface is enabled in arbitration master mode, but no external access is currently executed, the EBC is idle. During this idle state the external interface behaves in the following way: * The data port LD(15:0) is in high impedance state (floating).
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Local Bus Interface (LBI) * The address port LA(15:0) drives the address used last. * LRD/LWR remain inactive (High).
6.2.6
External Bus Arbitration
In high performance systems it may be efficient to share external resources like memory banks or peripheral devices among more than one bus controller. The LBI's EBC block supports this approach with the possibility to arbitrate the access to its external bus, i.e. to the external devices. This bus arbitration allows an external master to request the EBC's bus via the LHOLD input. The EBC acknowledges this request via the LHLDA output and will float its bus lines in this case. The new master may now access the peripheral devices or memory banks via the same interface lines as the EBC. During this time the MUNICH32X can continue executing internal processes, as long as it does not need access to the external bus. When the EBC needs access to its external bus while it is occupied by another bus master, the bus is requested via the LBREQ output. The external bus arbitration is enabled by setting bit HLDEN in the LBI Configuration register to `1'. This bit may be cleared during the execution of program sequences, where the external resources are required, but cannot be shared with other bus masters. In this case the EBC will not answer to LHOLD requests from other external masters. Note: The pins LHOLD, LHLDA and LBREQ maintain their functionality (bus arbitration) even after the arbitration function has been switched off by clearing HLDEN. All three pins are used for bus arbitration after bit HLDEN was set once. Entering the Hold State Access to the EBC's external bus is requested by driving its LHOLD input low. After synchronizing this signal the EBC will complete a current external bus cycle (if any is active), release the external bus and grant access to it by driving the LHLDA output low. During hold state the EBC manages the external bus interface as follows: * Address and data bus(es) float to tri-state. * Command lines become inputs (LRD, LWR, LBHE). Should the MUNICH32X require access to its external bus during hold mode, it activates its bus request output LBREQ to notify the arbitration circuitry. LHOLD is activated only during hold mode. It will be inactive during normal operation.
Data Sheet
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Local Bus Interface (LBI)
LHOLD (Input) LHLDA (Output) LBREQ (Output) LCSO (Output) Output Signals (LRD, LWR)
ITD10352
Figure 62
External Bus Arbitration (Releasing the Bus)
Note: The MUNICH32X will complete the currently running bus cycle before granting bus access as indicated by the dotted lines. This may delay hold acknowledge compared to this figure. The figure above shows the first possibility for LBREQ to become active. Exiting the Hold State The external bus master returns the access rights to the MUNICH32X EBC by driving the LHOLD input high. After synchronizing this signal the EBC will drive the LHLDA output high, actively drive the control signals and resume executing external bus cycles if required. Depending on the arbitration logic, the external bus can be returned to the EBC under two circumstances: * The external master does not require access to the shared resources and gives up its own access rights, or * The MUNICH32X EBC needs access to the shared resources and demands this by activating its LBREQ output. The arbitration logic may then deactivate the other master's LHLDA and hence free the external bus for the EBC, depending on the priority of the different masters.
Data Sheet
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Local Bus Interface (LBI)
LHOLD (Input) LHLDA (Output) LBREQ (Output) LCSO (Output) Output Signals (LRD, LWR)
ITD10353
Figure 63
External Bus Arbitration (Regaining the Bus)
The falling LBREQ edge marks the last moment for LBREQ to trigger the indicated regain-sequence. Even if LBREQ is activated earlier the regain-sequence is initiated by LHOLD going high. LBREQ and LHOLD are connected via an external arbitration circuitry. Note that LHOLD may also be deactivated without the EBC requesting the bus.
6.2.7
LBI Bus Arbitration
This section covers the LBI initialization when the MUNICH32X is operating in local bus Master mode or Slave mode, and the operation of bus mode transfers from hold to active state (and vice versa). Note that bus master mode means that the device is driving the local bus and performing bus cycles, and bus slave mode means that the EBC bus is in HOLD mode, and that an external controller may read the LBI Mailbox registers. On start-up, the MUNICH32X could be set to operate in LBI bus arbitration master mode (LCONF.ABM = `1') or LBI bus arbitration slave mode (LCONF.ABM = `0'). The arbitration master mode is chosen if the device needs to output the LHLDA signal. Note that LCONF.HDEN = `1' allows responding to the arbitration signals, whereas LCONF.HDEN = `0' causes this device not to give up its bus. This function can also be used by software or hardware during critical cycles.
6.2.7.1
Master/Slave Bus Arbitration
The master normally drives the LBI bus signals such as LALE (only in multiplexed mode), LWR and LRD. The slave is defined to input the LBI bus control signals (LALE,
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Local Bus Interface (LBI) LWR and LRD). Bus arbitration is required when the slave also needs to access LBI bus peripherals. For this purpose, the external busses of the master and the slave are directly connected together. However, it must always be assured that at one time only one of them, either the master or the slave, controls all external bus signals, while the other one drives its bus pins into an high-impedance state. This arbitration of the external bus is controlled by the low-level active pins LHOLD (hold request), LHLDA (hold acknowledge), and LBREQ (bus request) of the two devices. Note that the definition and function of the bus arbitration signals is different in master and slave mode. The following table describes these differences. Table 16 Pin LHOLD LBI Bus Arbitration Signals Direction Input Function in Master Mode While LHOLD is high, the master operates in normal mode. Upon a high-to-low transition, the master issues a hold request. The master backs off the bus, activates LHLDA and goes into hold mode. A low-to-high transition issues the exit from hold mode. The master deactivates LHLDA, takes over the bus and enters normal operation again. High during normal operation. When the master enters hold mode, it sets LHLDA to low after releasing the bus. On exit of hold mode, the master first sets LHLDA to high and then goes onto the bus again. High during normal operation. The master activates LBREQ by setting it to low earliest one TCL after activating LHLDA if it has to perform an external bus access. If the master has regained the bus, LBREQ is set to high one TCL after deactivation of LHLDA. Function in Slave Mode While both LHOLD and LHLDA are high, the slave is in hold mode, the bus interface is tristated. When the slave is released out of hold mode (LHLDA = 0) and has completely taken control over the external bus, a low level at this pins requests the slave to go into hold mode again. However, in any case the slave will perform at least one external bus cycle before going into hold mode again.
LHLDA
Output
LBREQ
Output
Pin LHOLD
Direction Input
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Local Bus Interface (LBI) LHLDA LBREQ Input Output A high-to-low transition at this pin releases the slave from hold mode. This signal is high as long as the slave operates from internal memory. When it detects that an external access is required, it sets LBREQ to low and waits for signal LHLDA to become low. LBREQ will go back to high when the slave has backed off the bus after it was requested to go into hold mode.
6.2.7.2
Initialization of the Master/Slave Bus Arbitration
Figure 64 shows the correct connection of the bus arbitration signals between the master and the slave. In order to provide correct levels during initialization of the master and the slave, two external pull-up devices are required. One is connected to the master's LHOLD input, the other to the slave's LHLDA input. Note: For compatibility reasons with existing applications, these pull-ups can not be integrated into the chip.
V CC
V CC
LHOLD
LHOLD
LHLDA MASTER LBREQ
LHLDA SLAVE LBREQ
ITD10354
Figure 64
Connection of the Master and Slave Bus Arbitration Signals
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Local Bus Interface (LBI) Bus Arbitration Master Initialization After reset, the master is normally starting execution out of external memory. During reset, the default is the arbitration slave mode. The master arbitration mode must first be selected done by setting the LCONF.ABM = `1'. During the initialization, the HDEN bit in register LCONF must be set. Since the LHOLD pin is held high through the external pullup, no hold requests can occur, even when the slave has not been initialized yet. Note that the HDEN bit of the master can be reset during normal operation to force the master to ignore hold requests from the slave until HDEN is set again. However, the pins LHOLD, LHLDA and LBREQ are still reserved for the bus arbitration. This is intended to have the option to disable certain critical processes against interruption through hold requests. Bus Arbitration Slave Initialization The slave must start using internal resources only after reset. During reset, the default mode is the slave mode. This is also done by programming the LCONF.ABM = `0'. This enables the slave mode of the bus arbitration signals. After this, the HDEN bit in register LCONF must be set. Note: 1. After setting the slave's HDEN bit, the LBREQ output of the slave might be activated to low for a period of 2TCL. If the master does not recognize this hold request (it depends on the master's transition detection time slot, whether this short pulse is detected), this pulse has no effect. If the master recognizes this pulse, it might go into hold mode for one cycle. 2. It is recommended to not reset the slave's HDEN bit after initialization.
6.2.7.3
Operation of the Master/Slave Bus Arbitration
The figure below shows the sequence of the bus arbitration signals in a master/slave system. The start-up condition is that the master is in normal mode and operating on the external bus, while the slave is in hold mode, operating from internal memory; the slave's bus interface is tristated. The marked time points in the diagram are explained in detail in the following. 1) The slave detects that it has to perform an external bus access. It activates LBREQ to low, which issues a hold request to the master. 2) The master activates LHLDA after releasing the bus. This initiates the slave's exit from hold sequence. 3a) When the master detects that it also has to perform external bus accesses, it activates LBREQ to low. The earliest time for the master to activate LBREQ is one TCL after the activation of the master's LHLDA signal. However, the slave will ignore this signal until it has completely taken over control of the external bus. In this way, it is assured that the slave will at least perform one complete external bus access.
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Local Bus Interface (LBI) 3b) If the master can operate from internal memory while it is in hold mode, it leaves the LBREQ signal high until it detects that an external bus access has to be performed. The slave therefore can stay on the bus as long as the master does not request the bus again. 4) When the master has requested the bus again through activation of its LBREQ signal, the slave will complete the current access and go into hold mode again. After completely tristateing its bus interface, the slave deactivates its LBREQ signal, thus releasing the master out of hold mode. 5) The master has terminated its hold mode and deactivates its LHLDA signal again. Now the master again controls the external bus again. 6) The master deactivates its LBREQ signal again one TCL after deactivation of LHLDA. From now on (and not earlier), the slave can generate a new hold request from the master. With this procedure it is assured that the master can perform at least one complete bus cycle before requested by the slave to go into hold mode again. Also shown in Figure 65 is the sequence of the bus control between the master and the slave.
1) M-LHOLD, S-LBREQ 4)
2) M-LHLDA, S-LHLDA
5)
3a) M-LBREQ, S-LHOLD
3b)
6)
Master on the Bus LBUS
Slave on the Bus
Master on the Bus
ITD10355
Figure 65
Bus Arbitration Sequence
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Local Bus Interface (LBI)
6.3
LBI Data Mode State Machine (DMSM)
The Data Mode State Machine (DMSM) in the Local Bus Interface will service the FIFOs in specific devices such as the Siemens ESCC2 (SAB 82532), FALC54 (PEB 2254) or HSCX (SAB 82525, SAB 82526). The state machine has user-programmable registers to correctly handshake with the peripheral to transfer data. The DMSM registers are directly accessible from the PCI host side. In the slave EBC mode, the Mailbox registers are accessible from the local bus side to facilitate communication between the PCI host system and the Local Bus host C. The MUNICH32X provides 4 DMA controllers to service two full duplex serial channels on the LBI (e.g., to connect an ESCC2). The Tx DMACs deliver DWORDs from the memory to the LBI TFIFO, and the Rx DMACs transfer the DWORDs from LBI RFIFO to the host memory. The EBC is responsible for `funneling' the DWORDs to the 8 or 16-bit local bus.
6.3.1
DMSM Function
The Data Mode State Machine (DMSM) services packet data from peripheral FIFOs and transfers them to the host memory via the DMACs. The DMSM assists in transferring data from peripheral devices based on the Siemens HDLC controller family (HSCX, ESCC2, FALC54). The procedure makes it easy for the software to transmit packets queued in the shared memory. Similarly, received packets are stored conveniently in the shared memory. The data transfers via the LBI interface are processed in two different modes: * Interrupt mode and * DMA assisted mode. The two modes can be selected for channel A/B by programming the bit fields LCONF.MDA/MDB of LBI Configuration register. Note that devices such as the ESCC2 and HSCX support both modes, whereas the FALC54 supports only the interrupt mode. The choice of a particular method will be application dependent.
6.3.2
Data Transfer in Interrupt Mode
In the interrupt mode of data transfer, the DMSM interrogates certain pre-defined interrupt status registers of the LBI peripherals (addressed by DMSM/LBI Indirect External Configuration registers LREG0 ... LREG5), and takes action based on the status of certain data FIFO related status bits. Note that all other status bits are ignored by the DMSM but passed on to the host via the interrupt queue. When an interrupt from a LBI peripheral is detected and not masked, the LBI Pass Trough Interrupt Vector is generated and written to the address specified in Peripheral Interrupt Queue Base Address (PIQBA) register.
Data Sheet
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Local Bus Interface (LBI) The structure of the LBI Pass Through Interrupt Vector is as follows: LBI Pass Through Interrupt Vector 31 LPT_IV 1 15 LPT_IV LSTAT IS(7:0) LBI Interrupt Status Contains the values of LSTAT LBI Status Register's bit field (7 ... 0) in all modes with automatic DMSM interrupt processing. In the case of no DMSM interrupt processing this bit field is constant `0' and the corresponding interrupt vector ID is LPTID = 0110B IS Interrupt Status Contains the Interrupt Status registers bit fields of the LBI peripheral (see table below). GIS Global Interrupt Status Contains the Global Interrupt Status registers bit fields of the LBI peripheral (see table below). LPTID LBI Pass Through Interrupt Vector ID Specifies the ID code for the different interrupt vectors (see table below). LPTID = 0110B is generated if no automatic interrupt processing by DMSM is selected in register LCONF. In this case bit field LSTAT is constant `0'. LSTAT(7:0) 0 0 0 LPTID(3:0) GIS(7:0) 0 16
LPTID(3:0) Coding 0000B 0001B 0010B 0011B 0110B
IS Contents GIS GIS GIS GIS 00H
GIS Contents ISR0A ISR1A ISR0B ISR1B 00H
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Local Bus Interface (LBI) Data Transfer Description As HDLC packets are received by the LBI peripheral, they fill into the RFIFO (threshold value must be programmed in register to be compliant to that of the external device). When the threshold is reached, the peripheral generates the RPF interrupt. The DMSM services then, depending on the threshold value, up to 32 data bytes, assembles them and alerts the DMA controller to transfer them to host memory. Each DMA access transfers as many DWORDs as possible (PCI burst size = 8 DWORD typically). At the end of the Rx packet, the RME interrupt is serviced, the RBCL byte count (bytes remaining in RFIFO) is determined and the receive bytes are serviced. Data is fetched and the valid number of bytes is indicated in the status word at the end of the DMA buffer. Similarly on the transmit side, when an XPR interrupt is detected, the DMSM requests the LBI DMA controller to take the Tx packet data. The LBI DMAC then delivers the data and stores it in the LBI TFIFO. When 32 bytes are available in the TFIFO, the DMSM transfers the 32 bytes to the peripheral, and sets the XTF bit in the peripheral to start sending out the packet. When the next XPR is indicated, the LBI DMA is alerted to fetch the next set of data, and the DMSM transfers it to the peripheral. When the Tx packet is completed, the DMAC indicates the number of valid bytes transferred. The DMSM transfers the valid bytes and sets the XTF and the XME bits to indicate to the peripheral HDLC controller to close the packet with the trailer bytes (CRC and Flag).This is implemented by the on-chip logic. Note that all LBI peripheral interrupts are maskable via the DMSM register LREG6.
6.3.3
Data Transfer in DMA Assisted Mode
Some devices such as ESCC2 and HSCX support DMA assisted data transfers from and to their internal FIFOs. If this function is chosen, the DMSM services the DMA request pins of the peripheral (DRQTA, DRQRA, DRQTB, DRQRB) and acknowledges the requests with the DACKTA, DACKRA, DACKTB and DACKRB pins. Note that the bit field LCONF.CDP in LBI Configuration register enables combined DMA acknowledge pins for receive and transmit direction of the LBI channels A/B (refer to register description section). The DMSM supports transferring of data to the LBI FIFO from the peripheral's FIFO. It also uses the DMSM registers (LREG0 ... LREG5) to set the peripheral's XTF and RMC bits to start and complete packet transfers. It recognizes RME and XPR interrupts and passes other interrupts.
6.3.4
DMSM Registers
If the DMSM has to control the interrupt driven data handling of only a single device such as the HSCX, the addresses of the device specific registers (e.g., XFIFOA, RMC bit location in CMDR register) could be fixed. However, the state machine is needed to handle different devices (HSCX, ESCC2, FALC54 etc.), which have the same registers
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Local Bus Interface (LBI) (e.g., XFIFO, CMDR), but located at different addresses. Hence it is necessary that the state machine uses an indirect pointer mechanism to address the required registers of the peripheral on the LBI. Refer to LBI register description LBI Registers for an overview of the DMSM register set. DMSM Register Initialization The user (PCI host CPU) initializes the DMSM registers with addresses of specific registers (e.g., XFIFOA address is 00H), and control bit positions of the peripheral that is attached as part of the configuration instructions. After initialization, no further software interaction with these registers is required. The control of the DMSM is handled by the LBI Configuration Register: * LCONF.LBIRES resets and keeps the DMSM in an initial state (same as hardware reset state). For normal DMSM operation bit LCONF.LBIRES must be set to `1' again. * LCONF.DCA: Ignore processing of channel A interrupts and pass everything to the interrupt queue. * LCONF.DCB: Ignore processing of channel B interrupts and pass everything to the interrupt queue. DMSM Suspend Mode PCI Direct Accesses to the peripheral registers are possible at any time (refer to Figure 56). If such an access is requested while the DMSM assisted data transfers are taking place, the DMSM will go into `suspend' mode after completing its current bus cycle and give up the bus to the Direct Access path. The PCI Direct Access cycle (read/write) may be extended, e.g. by using the TRDY signal. If the PCI Direct Access is requested while the LBI does not have `ownership' of the local bus (i.e., it is in slave mode), then the LBI will extend the PCI cycle until it is able to get the bus back and complete the PCI access cycle. The status of the LBI (master/slave mode) is indicated by an interrupt (via line LINTI1 or LINTI1 & LINTI2) and the bit field LCONF.ABM in LBI Configuration register.
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Local Bus Interface (LBI)
6.4
Peripheral Device Register Read/Write Operation
The local bus can work in 8/16-bit multiplexed/de-multiplexed mode. This 16-bit address space can be mapped into the host memory space using the base address initialized as part of device configuration. Other configuration parameters define the clock speed of the local bus, and the number of wait states to be used with the local bus, and also the number of wait states to be added to PCI cycles. Register Write to Peripherals A PCI write within the local bus address space causes the address and data to be transferred to the peripherals on the local bus. The TRDY (target ready) signal is delayed until the peripheral is ready to accept the write data. With this approach, consecutive PCI writes are possible to this address range. Register Read from Peripherals The local bus address space is mapped into the shared memory space, and hence a Read operation is similar to a read from memory or any memory mapped register. From the PCI host, this is a PCI Read cycle with pre-programmed number of wait cycles (0-15) for access to this address range. Within the local bus, the Read address is physically mapped into the 16-bit address of the local bus, and Read cycle is performed to the peripheral. A 8/16 bit data read takes place at the pre-programmed local bus speed, and the 8/16 bit data is then passed on to the PCI cycle with the correct number of BE (byte enable) bits set.
Data Sheet
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Local Bus Interface (LBI)
6.5
Connection to Common Peripherals
As described above, the DMSM is designed to work optimally with Siemens HDLC devices for efficient transfer of packet data. However, the PCI-to-local bus bridge may be used to connect any other peripheral device with a microprocessor interface. In this case the only function of the DMSM is to check interrupt signals LINTI1 and LINTI2 and to generate LBI pass through interrupt vectors which are transferred into peripheral interrupt queue. These interrupt vectors are of the constant value 86000000H and indicate that an LBI interrupt event occured (refer to Chapter 6.3.2) In the case that both LINTI input signals are used (LINTI2 enabled by bit LCONF.SPINT) simultaneous interrupt events may generate only one interrupt vector. The current status of signals LINTI1 and LINTI2 can be checked anytime by read access to LBI Status Register LSTAT. The signal polarity can be selected via bits HE1 and HE2 in LBI Configuration Register LCONF. The following bit settings in registers CONF and LCONF are appropriate to connect common peripherals:
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Local Bus Interface (LBI) Configuration Register CONF Offset Address 00H LBI = 0 LCD = n LBI MODE Select Must be set to `0' to disable DMSM DMA support functions of the LBI. LBI Timer/Clock Division Any value required for local bus operation
LBI Configuration Register LCONF Offset Address 40H
IPA
DCA = `1'
It is recommended to set this bit to `0' Disregards the Interrupts for Channel A Must be set to `1'; the DMSM will transfer all interrupt indications without any automatic evaluation of interrupt reasons. Disregards the Interrupts for Channel B Must be set to `1'; the DMSM will transfer all interrupt indications without any automatic evaluation of interrupt reasons. Mode Channel A Must be set to `0' to disable DMSM DMA functions. Mode Channel B Must be set to `0' to disable DMSM DMA functions. It is recommended to set this bit to `0' It is recommended to set this bit to `0' It is recommended to set this bit to `0' Reset LBI EBC Block Must be set to `1' to enable EBC operation Reset LBI DMSM Block Must be set to `1' to enable DMSM operation. Otherwise no interrupt vectors will be generated on LINTI1 and LINTI2 activity. It is recommended to set this bit field to 000B LINTI1 Polarity HE1 = `0' configures input signal LINTI1 for active high polarity HE1 = `1' configures input signal LINTI1 for active low polarity LINTI2 Polarity HE2 = `0' configures input signal LINTI2 for active high polarity HE2 = `1' configures input signal LINTI2 for active low polarity
DCB = `1'
MDA = `0' MDB = `0'
SDA DID CDP
EBCRES = `1' LBIRES = `1'
DV(2:0)
HE1
HE2
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Local Bus Interface (LBI) SPINT Seperate Interrupt Pins Must be set to `1' if LINTI2 interrupt input signal is used. Otherwise only signal LINTI1 will be evaluated by DMSM. These bits are to be configured depending on the local bus requirements. Refer to LCONF register description for details.
EALE HDEN BTYP(1:0) RDEN ABM MCTC(3:0)
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Local Bus Interface (LBI)
6.6
LBI DMA Controller (DMAC)
The LBI provides a 4-channel bi-directional DMA controller (2 channels Rx, 2 channels Tx). Note that for LBI channel A, the DMA signal lines in receive and transmit direction may be shared by setting the bit field LCONF.SDA. The direction is then controlled by the bit field LCONF.DID. The polling mechanism of the LBI DMAC differs from the serial PCM core DMAC. The LBI DMAC does not include the slow poll and hold poll functions of the serial PCM core DMAC, which is advantageous in this case, since the serial data traffic on the LBI can be highly asynchronous. A functionality similar to the POLL(31:0) bit fields of the TXPOLL register is implemented in the LBI Start Transfer register LTRAN, which provides two bit fields GOA and GOB for the two LBI channels. To initiate the LBI DMAC mode, the user has to setup a dummy descriptor with bit fields HOLD = `1', FE = `1' and NO = `0' for the required channel(s). If valid data are available in shared memory, the HOLD bit in that dummy descriptor must be reset and LTRAN.GOA/GOB must be programmed to `0'. From then on, each time the HOLD bit in Tx descriptor is reset by the host to continue a data transfer, the value of LTRAN.GOA/GOB must also be programmed to `0'. When a DMA related interrupt on the LBI is detected, the LBI DMA Interrupt Vector is generated and written to the address specified in LBI Tx Interrupt Queue Base Address (LTIQBA) register for transmit direction or LBI Rx Interrupt Queue Base Address (LRIQBA) register for receive direction. The structure of the LBI DMA Interrupt Vector is as follows:
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Local Bus Interface (LBI) LBI DMA Interrupt Vector 31 LDMA_IV 0 15 LDMA_IV 0 R/T 0 0 HI FI 0 0 ERR 0 FE2 0 0 0 0 1 1 R/T 0 0 0 0 00H 0 0 CHN 16
Rx/Tx Direction `1': LBI DMAC Receive Interrupt `0': LBI DMAC Transmit Interrupt
CHN
Channel Number `1': LBI DMAC Channel B Interrupt `0': LBI DMAC Channel A Interrupt
HI, FI, ERR, FE2 (Tx only)
Host Interrupt, Frame Interrupt, Error, Frame End For a detailed description, refer to Section 12.4: Interrupt Bit Field Definitions.
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Local Bus Interface (LBI)
Data Sheet
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Synchronous Serial Control (SSC) Interface
7
7.1
Synchronous Serial Control (SSC) Interface
Overview
The Synchronous Serial Control (SSC) interface provides a flexible high-speed serial communication link between the MUNICH32X and other microcontrollers or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication up to 8.25 MBaud (@ 33 MHz bus clock). The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible, or Microwire compatible devices. Transmission and reception of data is double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. The high-speed synchronous serial interface can be configured very flexibly, so it can be used with other synchronous serial interfaces (e.g., the ASC0 in synchronous mode), serve for master/slave or multimaster interconnections or operate compatible with the popular SPI interface. It allows communicating with shift registers (I/O expansion), peripherals (e.g. EEPROMs) or other controllers (networking). Data is transmitted or received on the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output or input on pin MCLK. These pins are implemented as alternate functions of the General Purpose Bus.
General Purpose Bus Control Alternate Functions GPDIR GPDATA Data Registers Control Registers Interrupt Control
SSCBR SSCTB SSCRB
SSCCON SSCCSE SSCIM
MCLK MTSR MRST GPDIR General Purpose Bus Direction Register GPDATA General Purpose Bus Data Register SSCBR SSCTB SSCRB SSC Baud Rate Generator/Reload Register SSC Transmit Buffer Register (write only) SSC Receive Buffer Register (read only)
SSC_IV SSCCON SSC Control Register SSCCSE SSC Chip Select Enable Register SSCIM SSC_IV SSC Interrupt Mask Register SSC Interrupt Vector
ITD10356
Figure 66
Registers and Port Pins Associated with the SSC
Data Sheet
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Synchronous Serial Control (SSC) Interface
CPU Clock
Baud Rate Generator
Clock Control Shift Clock
Slave Clock Master Clock
SCLK
Receive Int. Request Transmit Int. Request Error Int.Request
SSC Control Block
Status
Control MTSR Pin Control
16-Bit Shift Register
MRST
Transmit Buffer Register SSCTB
Receive Buffer Register SSCRB
Internal Bus
MCB01957
Figure 67
Synchronous Serial Channel SSC Block Diagram
The operating mode of the serial channel SSC is controlled by its bit-addressable control register SSCCON. This register serves for two purposes: * During programming (SSC disabled by SSCEN = `0') it provides access to a set of control bits, * During operation (SSC enabled by SSCEN = `1') it provides access to a set of status flags. A detailed control register description for each of the two modes is provided in Section 11.2.5. The shift register of the SSC is connected to both the transmit pin and the receive pin via the pin control logic (see block diagram). Transmission and reception of serial data is synchronized and takes place at the same time, i.e. the same number of transmitted bits is also received. Transmit data is written into the Transmit Buffer SSCTB. It is moved to the shift register as soon as this is empty. An SSC-master (SSCMS = `1') immediately starts transmitting, while an SSC-slave (SSCMS = `0') waits for an active shift clock.
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Synchronous Serial Control (SSC) Interface When the transfer starts, the busy flag SSCBSY is set and a transmit interrupt request (SSCTXI) will be generated to indicate that SSCTB may be reloaded again. When the programmed number of bits (2 ... 16) has been transferred, the contents of the shift register is moved to the Receive Buffer SSCRB and a receive interrupt request (SSCRXI) will be generated. If no further transfer is to take place (SSCTB is empty), SSCBSY will be cleared at the same time. Software should not modify SSCBSY, as this flag is hardware controlled. Note: Only one SSC can be master at a given time. The transfer of serial data bits may be programmed in many respects: * * * * * * The data width may be selected in a range between 2 bits and 16 bits. Transfer may start with the LSB or the MSB. The shift clock may be idle low or idle high. Data bits may be shifted with the leading or trailing edge of the clock signal. The baudrate may be set from 152 Baud up to 5 MBaud (@ 20 MHz CPU clock). The shift clock can be either generated (master) or received (slave).
This flexible programming allows to adapt the SSC to a wide range of applications, where serial data transfer is required. The Data Width Selection allows to transfer frames of any length, from 2-bit `characters' up to 16-bit `characters'. Starting with the LSB (SSCHB = `0') allows communicating e.g. with ASC0 devices in synchronous mode (C166 family) or 8051 like serial interfaces. Starting with the MSB (SSCHB = `1') allows to operate compatible with the SPI interface. Regardless which data width is selected and whether the MSB or the LSB is transmitted first, the transfer data is always right aligned in registers SSCTB and SSCRB, with the LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the internal shift register logic. The unselected bits of SSCTB are ignored, the unselected bits of SSCRB will be not valid and should be ignored by the receiver service routine. The Clock Control allows to adapt transmit and receive behaviour of the SSC to a variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out transmit data, while the other clock edge is used to latch in receive data. Bit SSCPH selects the leading edge or the trailing edge for each function. Bit SSCPO selects the level of the clock line in the idle state. Hence for an idle-high clock the leading edge is a falling one, a 1-to-0 transition. The figure below summarizes the clock control.
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Synchronous Serial Control (SSC) Interface
SSCPO SSCPH 0 0 1 1 0 1 0 1
Serial Clock SCLK
Pins MTSR / MRST First Bit Latch Data Shift Data
ITD10357
Transmit Data
Last Bit
Figure 68
Serial Clock Phase and Polarity Options
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Synchronous Serial Control (SSC) Interface
7.2 7.2.1
Operational Mode Full-Duplex Operation
The different devices are connected through three lines. The definition of these lines is always determined by the master: The line connected to the master's data output pin MTSR is the transmit line, the receive line is connected to its data input line MRST, and the clock line is connected to pin MCLK. Only the device selected for master operation generates and outputs the serial clock on pin MCLK. All slaves receive this clock, so their pin MCLK must be switched to input mode (GPDIR.p = `0'). The output of the master's shift register is connected to the external transmit line, which in turn is connected to the slaves' shift register input. The output of the slaves' shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave. The external connections are hard-wired, the function and direction of these pins is determined by the master or slave operation of the individual device. When initializing the devices in this configuration, select one device for master operation (SSCMS = `1'), all others must be programmed for slave operation (SSCMS = `0'). Initialization includes the operating mode of the device's SSC and also the function of the respective port lines (refer to section `Port Control').
Master Device #1 MTSR Shift Register MRST CLK Transmit Receive Clock Device #2 MTSR MRST Shift Register Slave
Clock
CLK Device #2 MTSR MRST
Clock Slave
Shift Register
CLK
Clock
ITS10358
Figure 69
SSC Full Duplex Configuration
Note: The shift direction applies to MSB-first operation as well as to LSB-first operation.
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Synchronous Serial Control (SSC) Interface The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration. During a transfer each slave shifts out data from its shift register. There are two ways to avoid collisions on the receive line due to different slave data: 1. Only one slave drives the line, i.e. enables the driver of its MRST pin. All the other slaves have to program there MRST pins to input. So only one slave can put its data onto the master's receive line. Only receiving of data from the master is possible. The master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. The selected slave then switches its MRST line to output, until it gets a deselection signal or command. 2. The slaves use open drain output on MRST. This forms a Wired-AND connection. The receive line needs an external pullup in this case. Corruption of the data on the receive line sent by the selected slave is avoided, when all slaves which are not selected for transmission to the master only send `1s'. Since this high level is not actively driven onto the line, but only held through the pullup device, the selected slave can pull this line actively to a low level when transmitting a zero bit. The master selects the slave device, from which it expects data either by separate select lines, or by sending a special command to this slave. After performing all necessary initializations of the SSC, the serial interfaces can be enabled. For a master device, the alternate clock line will now go to its programmed polarity. The alternate data line will go to either `0' or `1', until the first transfer will start. After a transfer the alternate data line will always remain at the logic level of the last transmitted data bit. When the serial interface is enabled, the master device can initiate the first data transfer by writing the Tx data into Tx Buffer Register SSCTB. This value is copied into the shift register (which is assumed to be empty at this time), and the selected first bit of the Tx data will be placed onto the MTSR line on the next clock from the Baudrate Generator (transmission only starts, if SSCEN = `1'). Depending on the selected clock phase, a clock pulse will also be generated on the MCLK line. With the opposite clock edge the master at the same time latches and shifts in the data detected at its input line MRST. This `exchanges' the Tx data with the Rx data. Since the clock line is connected to all slaves, their shift registers will be shifted synchronously with the master's shift register, shifting out the data contained in the registers, and shifting in the data detected at the input line. After the preprogrammed number of clock pulses (via the data width selection) the data transmitted by the master is contained in all slaves' shift registers, while the master's shift register holds the data of the selected slave. The contents of the shift register of the master and all slaves are copied into the Rx Buffer Register SSCRB and the Rx interrupt flag SSCRXI is set. A slave device will immediately output the selected first bit (MSB or LSB of the transfer data) at pin MRST, when the contents of the Tx buffer are copied into the slave's shift register. It will not wait for the next clock from the baudrate generator, as the master does. The reason is that, depending on the selected clock phase, the first clock edge
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Synchronous Serial Control (SSC) Interface generated by the master may already be used to clock in the first data bit. Hence the slave's first data bit must already be valid at this time. Note: On the SSC always a transmission and a reception takes place at the same time, regardless whether valid data has been transmitted or received. This is different, e.g., from asynchronous reception on ASC0. The initialization of the MCLK pin on the master requires some attention in order to avoid undesired clock transitions, which may disturb the other receivers. The state of the internal alternate output lines is `1' as long as the SSC is disabled. This alternate output signal is ANDed with the respective port line output latch. Enabling the SSC with an idlelow clock (SSCPO = `0') will drive the alternate data output and (via the AND) the port pin MCLK immediately low. To avoid this, use the following sequence: * * * * * select the clock idle level (SSCPO = `x'), load the port output latch with the desired clock idle level (GPDATA.p = `x'), switch the pin to output (GPDIR.p = `1'), enable the SSC (SSCEN = `1'), and if SSCPO = `0': enable alternate data output (GPDATA.p = `1').
The same mechanism as for selecting a slave for transmission (separate select lines or special commands) may also be used to promote the role of the master to another device in the network. In this case the previous master and the future master (previous slave) will have to toggle their operating mode (SSCMS) and the direction of their port pins (see description above). Chip Select Control There are 4 chip select pins associated with the SSC port: MCS0 to MCS3. The four chip select lines are automatically activated at the beginning of a transfer and deactivated again after the transfer has ended. Activation of a chip enable line always begins one half bit time before the first data bit is output at the MTSR pin, and the deactivation (except for the continuous transfers) is performed one half bit time after the last bit of the transfer has been transmitted/received completely. The chip select lines are selected by the control bits ASEL0 to ASEL3 of the SSC Chip Select Enable Register SSCCSE (refer to Chapter 11.2.5). By setting any of these bits to 0, the corresponding chip select port will be asserted when transmitting data. All other bits of the SSCCSE register have to be set to `0'.
7.2.2
Half Duplex Operation
In a half duplex configuration only one data line is necessary for both receiving and transmitting of data. The data exchange line is connected to both pins MTSR and MRST of each device, the clock line is connected to the MCLK pin.
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Synchronous Serial Control (SSC) Interface The master device controls the data transfer by generating the shift clock, while the slave devices receive it. Due to the fact that all transmit and receive pins are connected to the one data exchange line, serial data may be moved between arbitrary stations. Similar to full duplex mode there are two ways to avoid collisions on the data exchange line: * only the transmitting device may enable its Tx pin driver * the non-transmitting devices use open drain outputs and only send ones. Since the data inputs and outputs are connected together, a transmitting device will clock in its own data at the input pin (MRST for a master device, MTSR for a slave). This allows to detect any corruptions on the common data exchange line, where the Rx data is not equal to the Tx data.
Master
Device #1 MTSR
Device #2 MTSR MRST Clock
Slave
Shift Register
MRST CLK
Shift Register
Clock
CLK Common Transmit / Device #3 Receive Line MTSR MRST
Clock Slave
Shift Register
CLK
Clock
ITS10359
Figure 70
SSC Half Duplex Configuration
Continuous Transfers When the transmit interrupt request flag is set, it indicates that the Tx Buffer Register SSCTB is empty and ready to be loaded with the next transmit data. If SSCTB has been reloaded by the time the current transmission is finished, the data is immediately
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Synchronous Serial Control (SSC) Interface transferred to the shift register and the next transmission will start without any additional delay. On the data line there is no gap between the two successive frames. For example, two byte transfers would look the same as one 16-bit word transfer. This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer. The length of a total data frame is up to the software. This option can also be used to interface to byte-wide and word-wide devices on the same serial bus. Note: This feature only applies to multiples of the selected basic data width, since it would require disabling/enabling of the SSC to re-program the basic data width on-the-fly. Port Control The SSC uses three pins of the General Purpose Bus pins to communicate with the external world. Pin GP15/MCLK serves as the clock line, while pins GP13/MRST (Master Receive/Slave Transmit) and GP14/MTSR (Master Transmit/Slave Receive) serve as the serial data I/O lines. The operation of these pins depends on the selected operating mode (master or slave). In order to enable the alternate output functions (in this case SSC functions) of these pins instead of the general purpose I/O operation, the respective port latches of the General Purpose Bus registers (refer to Chapter 11.2.1) have to be set to `1', since the port latch outputs and the alternate output lines are ANDed. When an alternate data output line is not used (function disabled), it is held at a high level, allowing I/O operations via the port latch. The direction of the port lines depends on the operating mode. The SSC will automatically use the correct alternate input or output line of the ports when switching the modes. The direction of the pins, however, must be programmed by the user, as shown in Table 17. Using the open drain output feature helps to avoid bus contention problems and reduces the need for hardwired hand-shaking or slave select lines. In this case it is not always necessary to switch the direction of a port pin. The table below summarizes the required values for the different modes and pins. Table 17 Pin Function GP15/MCLK GP14/MTSR GP13/MRST GP15/MCLK SSC Clock Output SSC Data Output SSC Data Input SSC Clock Input Port Control of the SSC Interface Master Mode Port Latch Direction GPDATA.15 = `1' GPDIR.15 = `1' GPDATA.14 = `1' GPDIR.14 = `1' GPDATA.13 = `x' GPDIR.13 = `0' Slave Mode GPDATA.15 = `x' GPDIR.15 = `0'
Data Sheet
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Synchronous Serial Control (SSC) Interface Table 17 Pin Function GP14/MTSR GP13/MRST SSC Data Input SSC Data Output Port Control of the SSC Interface Master Mode Port Latch Direction GPDATA.14 = `x' GPDIR.14 = `0' GPDATA.13 = `1' GPDIR.13 = `1'
Note: An `x' means that the actual value is irrelevant in the respective mode. However, it is recommended to set these bits to `1' to make sure they are already in the correct state when switching between master and slave mode.
Data Sheet
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Synchronous Serial Control (SSC) Interface
7.3
Baud Rate Generation
The SSC interface has its own dedicated 16-bit baud rate generator with 16-bit reload capability, allowing baud rate generation independent from timers. The baud rate generator is clocked with the CPU clock divided by 2 (10 MHz @ 20 MHz bus clock). The timer is counting downwards and can be started or stopped through the global enable bit SSCEN in the SSC Control Register SSCCON. The register SSCBR (refer to Chapter 11.2.5) is the dual-function Baud Rate Generation Register. Reading SSCBR, while the SSC is enabled, returns the contents of the timer. Reading SSCBR, while the SSC is disabled, returns the programmed reload value. In this mode the desired reload value can be written to SSCBR. The formulas below calculate either the resulting baud rate for a given reload value, or the required reload value for a given baudrate:
fCPU
BaudrateSSC = 2 x ( + 1) SSCBR = (
fCPU
2 x BaudrateSSC )-1
represents the contents of the reload register, taken as unsigned 16-bit integer.
Data Sheet
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Synchronous Serial Control (SSC) Interface
7.4
Error Detection
The SSC is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes, while Transmit Error and Baudrate Error only apply to slave mode. When an error is detected, the respective error flag is set. When the corresponding error enable bit is set, also an error interrupt request will be generated by setting SSCERI (see Figure 71). The error interrupt handler may then check the error flags to determine the cause of the error interrupt. The error flags are not reset automatically (like SSCERI), but rather must be cleared by software after servicing. This allows to service some error conditions via interrupt, while the others may be polled by software. Note: The error interrupt handler must clear the associated (enabled) errorflag(s) to prevent repeated interrupt requests. A Receive Error (Master or Slave mode) is detected, when a new data frame is completely received, but the previous data was not read out of the Receive Buffer register SSCRB. This condition sets the error flag SSCRE and, when enabled via SSCREN, the error interrupt request flag SSCERI. The old data in the receive buffer SSCRB will be overwritten with the new value and is unretrievably lost. A Phase Error (Master or Slave mode) is detected, when the incoming data at pin MRST (master mode) or MTSR (slave mode), sampled with the same frequency as the CPU clock, changes in a range between one sample before and two samples after the latching edge of the clock signal (refer to section `Clock Control'). This condition sets the error flag SSCPE and, when enabled via SSCPEN, the error interrupt request flag SSCERI. A Baud Rate Error (Slave mode) is detected, when the incoming clock signal deviates from the programmed baud rate by more than 100%, i.e., it has a value of either more than double or less than half of the expected baud rate. This condition sets the error flag SSCBE and, when enabled via SSCBEN, the error interrupt request flag SSCEIR. Using this error detection capability requires that the slave's baud rate generator is programmed to the same baud rate as the master device. This feature allows to detect false additional, or missing pulses on the clock line (within a certain frame). Note: If this error condition occurs and bit SSCAREN = `1', an automatic reset of the SSC will be performed. This is done to reinitialize the SSC, when too few or too many clock pulses have been detected. A Transmit Error (Slave mode) is detected, when a transfer was initiated by the master (shift clock gets active), but the transmit buffer SSCTB of the slave was not updated since the last transfer. This condition sets the error flag SSCTE and, when enabled via SSCTEN, the error interrupt request flag SSCERI. If a transfer starts while the transmit buffer is not updated, the slave will shift out the `old' contents of the shift register, which are usually the data received during the last transfer. This may lead to the corruption of the data on the transmit/receive line in half-duplex mode (open drain configuration), if this slave is not selected for transmission. This mode
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Synchronous Serial Control (SSC) Interface requires that slaves not selected for transmission only shift out `ones', i.e. their transmit buffers must be loaded with `FFFFH' prior to any transfer. Note: A slave with push/pull output drivers, which is not selected for transmission, will normally have its output drivers switched. However, in order to avoid possible conflicts or misinterpretations, it is recommended to always load the slave's transmit buffer prior to any transfer.
Register SSCCON SSCTE Transmit Error SSCTE &
Register SSCIM
SSCRE Receive Error SSCRE
& >1 IMER ERI & Error Interrupt SSCEINT
SSCPE Phase Error SSCPE
&
Interrupt Vector SSC_IV SSCBE &
ITS10360
Baudrate Error
SSCBE
Figure 71
SSC Error Interrupt Control
Data Sheet
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Synchronous Serial Control (SSC) Interface
7.5
SSC Interrupt Control
The SSC generates three types of interrupts: transmit, receive and error interrupts. Any of these interrupts can be enabled by setting the corresponding bit of the SSC Interrupt Mask Register SSCIM (refer to Chapter 11.2.5) to `1'. All other bits of this register have to be set to zero. SSC Interrupt Vector 31 SSC_IV 1 15 SSC_IV R/T IV(15:0) Receive/Transmit Direction 0: Transmit direction 1: Receive direction D/E Data/Error Interrupt 0: Error interrupt 1: Data interrupt RXI ERI TXI IV Rx Interrupt 1: Indicates receive interrupt Error Interrupt 1: Indicates error interrupt Tx Interrup 1: Indicates transmit interrupt. Interrupt Vector Three different values: RXI = 1: Contents of SSC Receive Buffer Register. ERI = 1: Contents of SSC Control Register. TXI = 1: 0000H Example: 1. Transmit: SSC_IV(31 : 0) = A0010000H 0 1 0 0 0 0 R/T D/E 0 0 0 0 16 ERI RXI TXI 0
Data Sheet
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Synchronous Serial Control (SSC) Interface 2. Error: 3. Receive: SSC_IV(31:16) = A004H SSC_IV(15:0): contents of SSC Control Register SSCCON SSC_IV(31:16) = A002H SSC_IV(15:0): contents of SSC Rx Buffer Register SSCRB
Data Sheet
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IOM(R)-2 Interface
8
IOM(R)-2 Interface
The MUNICH32X contains an integrated IOM(R)-2 handler for driving ISDN Layer-1 devices via the serial PCM interface. Figure 72 shows an application with the MUNICH32X driving 8 S/T Basic Rate Interfaces via 2 QUAT(R)-S, PEB 2084, ISDN devices. All D-Channel and B-Channel packet processing is handled through the MUNICH32X using 24 HDLC channels operating directly on the host memory (no difference to normal HDLC operation).
CPU
Memory Channel 0 B1 B2 D
PCI Bus 32
DRDY 0 S/T QUAT -S PEB 2084
R
MUNICH32X SSC EEPROM
...
3
IOM -2 Interface 4 S/T QUAT -S PEB 2084
R
R
Channel 0 B1 B2
MON D C/I M
Channel 7 B1 B2
...
MON D C/I M
ITS10450
7
Figure 72
8 S/T Interfaces realized by one MUNICH32X and two QUAT(R)-S
Data Sheet
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IOM(R)-2 Interface
8.1
(R)
General Features
The IOM -Revision-2 (IOM(R)-2) standard defines an industry standard serial bus for interconnecting telecommunications ICs. The standard covers line card, NT1, and terminal architectures for ISDN and analog loop applications. In digital telephone switches, an inter-chip communication bus is often used to connect the codec/filter ICs to the switch backbone. Typically, a separate serial bus is used between each codec/filter IC and a line-card controller IC. The line card controller provides the connection to the switch backbone, as well as an interface to the microprocessor that controls the line card. The inter-chip bus structures that were used in this single channel per line pre-ISDN (Integrated Services Digital Network) telephone equipment are not well-suited for the 2 B + D structure of ISDN. To address this problem, four major European telephone equipment manufacturers jointly defined a new interface bus. These four companies, Alcatel, Italtel, Plessey, and Siemens invented a bus structure that satisfied the requirements of both ISDN and analog applications. The General Circuit Interface, or GCI, is an evolution of the ISDN Oriented Modular Interface (IOM(R)) invented by Siemens. The GCI was designed with the specific needs of interconnecting components on switch line cards. As such, it is not well-suited for terminal and NT1 applications. As a result, a terminal version of the interface has been designed. The terminal version has been designated the Special Circuit Interface T, or SCIT. The GCI line card and SCIT terminal bus specifications combined form the IOM(R) Revision 2 standard (IOM(R)-2). The MUNICH32X contains an integrated IOM(R)-2 handler for driving ISDN Layer-1 devices via the serial PCM interface. In this mode, the PCM interface has a structure and features of the IOM(R)-2 interface: * It is compatible with the IOM(R)-2 industry standard for line cards/trunk cards (supporting the Monitor and C/I communication channels), Figure 73. * Its 4 lines correspond to TXD/DU, RXD/DD, DCL, FSC of other ISDN devices. * The data rate is programmable up to 4.096 Mbit/s. * The clock frequency is either equal to the data rate, or twice the data rate. By default it is equal to the data rate.
Data Sheet
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IOM(R)-2 Interface
125 s FSC DCL DU DD
IOM CH0 IOM CH0
R
R
CH1 CH1
CH2 CH2
CH3 CH3
CH4 CH4
CH5 CH5
CH6 CH6
CH7 CH7
CH0 CH0
B1
B2
MONITOR
D
C/I
MM RX
ITD04319
Figure 73
IOM(R)-2 Interface with 2.048 Mbit/s Data Rate
8.1.1
B-Channels
The B1- and B2-channels are physically the first two 8-bit time slots after the frame sync pulse. Each B-channel carries 64-Kbit/s of user data (or digitized voice).
8.1.2
D-Channel
The D-channel contains 2 bits per frame, providing a 16-Kbit/s channel for carrying ISDN D-channel data. (In analog line-card applications of IOM(R)-2, there is no D-channel).
8.1.3
Monitor Channel (including MX, MR bits)
The monitor channels provide an interface between the microprocessor, via the line-card controller (line-card applications) or the IOM(R)-2 bus master (terminal applications), and devices attached to the bus. This allows these devices to be designed without their own microprocessor interface. Each channel consists of 8 bits of data and two associated handshake bits, MX and MR (monitor transmit and receive). The handshake procedure is described in the Chapter 8.2.1.
8.1.4
Command/Indicate Channel
The Command/Indicate channel (C/I) carries real-time status information between a line transceiver and the MUNICH32X.
Data Sheet
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IOM(R)-2 Interface Status information transmitted over the C/I channel is "static" in the sense that a 4-bit word is repeatedly transmitted, every frame, as long as the status condition that it indicates is valid. In general, the receiver monitors the C/I channel for changes in status. The definition and usage of the 4-bit C/I codes is described in the Chapter 8.2.2.
Data Sheet
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IOM(R)-2 Interface
8.2
IOM(R)-2 Handler
The built-in IOM(R)-2 handler processes the C/I and MONITOR channels of the IOM(R)-2 protocol; i.e. 8 independent IOM(R)-2 channels (subframes). It also supports the Dchannel access (priority control) on the S/T interface via the DRDY input line (Figure 72).
8.2.1
Monitor Handler
Handshake Procedure The monitor channel is full duplex and operates on a pseudo-asynchronous basis, that is, while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the MX and MR bits. For example: data is placed onto the monitor channel and the MX bit is activated. This data will be transmitted repeatedly (once per 8-kHz frame) until the transfer is acknowledged via the MR bit. Thus, the data rate is not 8-kbytes/s. Figure 74 illustrates the flow of events, and Figure 75 and Figure 18 show the timing. Idle The MX and MR pair being held inactive for two or more frames constitutes the channel being idle in that direction. The data (logical "high", i.e. negative logic) received in the monitor channel is invalid and should be "11111111". Start of Transmission The first byte of data is placed on the bus and MX is activated (low). MX remains active, and the data remains valid until an inactive-to-active transition of MR is received, indicating that the receiver has read the data off the bus. Subsequent transmission (general case Figure 75). - In the case of the second byte transfer the transmitter detects the MR bit transition from the inactive to the active state before transmitting the new second byte. At the time that a new byte is transmitted, MX is returned inactive for one frame time only (MX inactive for more than one frame time indicates an end of message), the data is valid in the same frame. In the following frame MX returns active again and the same data is transmitted. Data is repeated in subsequent frame and MX remains active until acknowledgement is detected (MR transition from inactive to active). Only packets with a multiple of two bytes length can be transmitted via the monitor channel (refer to registers IOMCON1 and IOMTMO).
Data Sheet
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IOM(R)-2 Interface First Byte Reception At the time the receiver sees the first byte, indicated by the inactive-to-active transition of MX, MR is by definition inactive. When the receiver is ready to acknowledge the first byte MR is activated. MR remains active until the next byte is received or an end of message is detected (MX held inactive for two or more frame times). Subsequent Reception The receiver acknowledges the receipt of a valid data by the transition of MR bit from the active to the inactive state for one frame followed by the transition to the active state in the next frame (Note: Validity of the data, including the first byte, can optionally be checked by the receiver applying a double-last-look criterion on each received data.) The reception of data is terminated by the receipt of an end-of-transmission indication (MX remaining inactive for two or more frame times). End of Transmission (EOM) - The transmitter after receiving a successful last byte acknowledge will indicate EOM by the transition of the MX bit from the active to inactive state followed by the persistence of the inactive state for at least one more frame. The contents of the monitor channel will become invalid in the same frame as the transition of the MX bit occurs. The invalid data should be "11111111". The sender is then in the idle state. Abort - The abort is a signal from the receiver to the transmitter indicating that data has been missed. It is not an abort in the classical sense, which is an indication from the transmitter that the current message should be ignored. The receiver indicates an abort by holding MR inactive for two or more frames in response to MX going active. Flow Control - The receiver can hold off the transmitter by keeping MR active until the receiver is ready for the next byte. The transmitter will not start the next transmission cycle until MR goes inactive. Time-Out - For the cases where no device acknowledges a data, or where the transmitter is unable to resume transmission, an optional time-out may be implemented.
Data Sheet
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IOM(R)-2 Interface
Receiver
MX
Transmitter
MR
MX, MD (1 st Byte)
MR
1 st Byte Byte Acknowledge 2 nd Byte
MX, MD (2 nd Byte) MX, MD (2 nd Byte)
MR
Transmission
MR
Byte Acknowledge n th Byte
te) MX, MD (n th By te) MX, MD (n th By
MR MR
Byte Acknowledge End of Transmission (EOM)
MX MX
MR MR
End of Transmission
ITD00255
Figure 74
Monitor Handshake Procedure
MX: monitor transmit bit, active low MR: monitor receive bit, active low MD: monitor data
Data Sheet
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IOM(R)-2 Interface
1st Byte
2nd Byte
n th Byte
MX Transmitter MX Latch Data MR Receiver MR
~ ~ ~ ~ ~ ~ ~ ~
EOM Latch Data Latch Data
~ ~
ACK 1st Byte nx 125 s
ACK 2nd Byte 125 s
ACK n th Byte
ITD00519
Figure 75
Monitor Handshake Timing in General
MX Transmitter MX New Byte
EOM
MR Receiver MR
~ ~
Abort Request
ITD00520
Table 18
Abort Request from Receiver
Data Sheet
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IOM(R)-2 Interface
8.2.2
C/I Channel Operation
The C/I channel is used to communicate real time status information and maintenance commands, such as loopback requests, link activation/deactivation procedures, and switch hook/ground key detection (voice channels). Data on the C/I channel is continuously transmitted in each frame until new data is to be sent. In this way, the C/I channel can be thought of as a set of static status lines that only change when the status changes. Data Integrity Where data integrity is a concern, a change in C/I channel data may be considered valid if it has been received in two consecutive frames. Command/Indication Codes (C/I) Codes The following is a description of the different commands and indications that are used over the IOM(R)-2 interface for signaling and control in ISDN systems. Table 19 Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 C/I Codes TXD (DD) DR RES TM2 TM1 - - - UAR AR AR2 ARL AR4 AI - - DC RXD (DU) TIM RES - - RSY - - UAI AR - - - AI - - DI
Note: The complete IOM(R)-2 register set is introduced in Section 11.2.6
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IOM(R)-2 Interface Table 20 List of Commands and Indications Abbreviation AI AI8 AI10 AI2 AIL AR AR8 AR10 AR2 ARL AR4 DC DI DR PU RES RSY SLIP TIM TM1 TM2 UAI UAR
Commands and Indications Activation Indication Activation Indication priority 1 Activation Indication priority 2 Activation Indication test loop 2 Activation Indication local test loop Activation Request Activation Request priority 1 Activation Request priority 2 Activation Request test loop 2 Activation Request local test loop Activation Request test loop 4 Deactivation Confirmation Deactivation Indication Deactivation Request Power Up Reset Resynchronization (loss of framing) Slip detected in framing Timing required (to activate IOM(R)-2) Test Mode 1 Test Mode 2 U only Activation Indication U only Activation Request
8.2.3
D-Channel Priority Control
In an application where the MUNICH32X represents a terminal (TE) interfaced to an Sbus via an S/T interface transceiver like the QUAT(R)-S (PEB 2081) and a multipoint configuration is implemented (i.e. more than one terminal is hooked up to one S-bus), the D-channel access has to be organized solving collision conditions. This D-channel access control is specified in ITU I.430. A data collision may occur during the MUNICH32X starts sending a packet over the D-channel. This collision is detected by the S/T interface transceiver and reported to the MUNICH32X by asserting the DRDY pin. Every time a D-channel collision occurs, this event is reported to the protocol controller. The transmit line (DU) sends continuous `1's. A "Late Stop" interrupt is generated and stored in the PCM Tx Interrupt Queue, indicating, that the current frame has to be retransmitted (refer to PCM Core Interrupt Bit Field description, chapter 12.4) in case of destructive collision of transmit data.
Data Sheet
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IOM(R)-2 Interface
8.3 8.3.1
IOM(R)-2 Interrupt Vector Description Monitor Interrupt Vector
31 16 0 0 1 0 0 0 DIR 0 0 1 1 1 Value(2:0) 0 0 0 0 1 7 Received Byte1 Received Byte0 0 0 1 0 0 0 1 0 0 0 0 1 0 CNO(2:0)
IOMM_IV
1
Monitor Transmit FIFO Empty (MTFE) Monitor Abort (MAB) Monitor Receive FIFO Full (MRFF) Monitor End of Message (MEM) Active Monitor Channel Found (AMCF) 15 IOMM_IV DIR
Interrupt upon Receive or Transmit Data Direction `0': Transmit `1': Receive
CNO(2:0)
Channel Number
8.3.2
C/I Interrupt Vector
31 16 0 0 1 0 0 0 1 0 0 0 0 1 CNO(2:0) 0 0 0 0 0 0 0 0 0 0 0 0 CIC(3:0)
IOMCI_IV
1 15
IOMCI_IV CNO(2:0) CIC
Data Sheet
0
Channel Number Current Indication Code (C/I Value)
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General Purpose Port
9
General Purpose Port
This 16-bit port may be used for general purpose I/O. It also provides alternate functionality to support LBI and SSC operations. The General Purpose Bus consists of two separate 8-bit ports, that can be individually selected to be general purpose or to provide the alternate function, i.e., each port line has a programmable alternate input or output function associated with it. The alternate function of the low 8-bit port is to provide DMA support pins (selected by setting Configuration register's bit field CONF.LBI), and the alternate function of high 8-bit port is to provide Synchronous Serial Control (SSC) interface support (selected by setting Configuration register's bit field CONF.SSC). Additionally, if CONF.LBI is selected, the DMA Tx/Rx acknowledge pins may be combined for each channel A/B. This is performed by setting LBI Configuration register's bit field LCONF.CDP. Note that the pin configuration for general purpose or alternate function mode is shown in Figure 78 on Page 238. Within each 8-bit port, all input/output lines are individually (bit-wise) programmable as inputs or outputs via the General Purpose Bus Direction register GPDIR. The General Purpose Bus is a true bi-directional port which is switched to high impedance state when configured as input. The output drivers of the port are push/pull drivers. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured as input or output. A write operation to a general purpose pin configured as an input (GPDIR.x = `0') causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A read-modify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. Writing to a general purpose pin configured as an output (GPDIR.x = `1') causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. If an alternate output function of a General Purpose Bus pin is to be used, the direction of this pin must be programmed for output (GPDIR.x = `1'); otherwise the pin remains in high-impedance state and is not effected by the alternate output function. The respective port latch should hold a `1', because its output is ANDed with the alternate output data. If an alternate input function of a General Purpose Bus pin is used, the direction of the pin must be programmed for input (GPDIR.x = `0'), if an external device is driving the pin. On reset, the input direction is default. If no external device is connected to the pin, however, the direction for this pin may also be set to output. In this case, the pin reflects the state of the port output latch. Thus, the alternate input function reads the value stored
Data Sheet
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General Purpose Port in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. There is one basic structure for all port lines providing only an alternate input function. Port lines providing only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether or not the pin is in alternate function mode accessible by user software. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. in order to avoid undesired transitions on the output pins when using port pins for general purpose output, the initial output value should be written to the port latch prior to enabling the output drivers. Note that the General Purpose Bus has its own interrupt vector associated with it, which is generated when an interrupt of a peripheral on this bus is detected. Interrupts on the General Purpose Bus are enabled by setting Configuration register's bit CONF.GIEN. General Purpose Bus Interrupt Vector 31 GP_IV 1 15 GP_IV GPH GPH(7:0) GP High Byte Interrupt Vector CONF.SSC = `0': Contains the user defined interrupt information of the high byte port of the General Purpose Bus (pins GP(15:8)). CONF.SSC = `1': 00H GPL GP Low Byte Interrupt Vector CONF.LBI = `0': Contains the user defined interrupt information of the low byte port of the General Purpose Bus (pins GP(7:0)). CONF.LBI = `1': 00H GPL(7:0) 0 0 0 0 1 0 1 00H 0 16
Data Sheet
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Reset and Initialization
10
10.1
Reset and Initialization
Reset
An external low signal on RST resets the MUNICH32X. It immediately switches all outputs to the high impedance state, with exception of pin TXDEN, which is driven high in that case. The alternate function pins are set to general purpose pins. All registers are set to their reset values. All functions are initialized to known states. After RST is deasserted and all clock/frame signals are active, the subfunctions PCI, Global Registers, Serial PCM Core, LBI EBC/Mailbox, LBI DMSM, LBI DMAC, SSC and IOM(R)-2 are in reset or standby mode. Status after Hardware Reset Table 21 Subfunction PCI interface Global Registers Subfunction Status after Hardware Reset Reset Status standby PCI config space registers accessible standby Slave registers accessible; General Purpose Bus enabled! standby Slave registers accessible reset Slave registers fixed to reset values standby Slave registers accessible standby Slave registers accessible standby Slave registers accessible; RXCLK (DCL), RXD (DD) and RSP (FSC) are connected; TXD (DU) is connected to Serial PCM core only
Serial PCM Core LBI EBC/Mailbox/DMSM LBI DMA Controller SSC IOM(R)-2
Data Sheet
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Reset and Initialization Accessing Subfunctions after Hardware Reset The functions LBI EBC, LBI DMSM, SSC, and IOM(R)-2 must be made accessible by additional programming before they can be used. Note that LBI functions are only available, if the DEMUX pin is set to `0' (PCI Interface Mode). The Table 22 shows the programming required to access the MUNICH32X subfunctions. Table 22 LBI EBC/ Mailbox LBI DMSM Programming after Hardware Reset * bit LCONF.EBCRES must be set to `1' * bit CONF.LBI must be set to `1' * bit LCONF.LBIRES must be set to `1'
Subfunction Required Register Programming
Data Sheet
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Reset and Initialization Table 22 SSC Programming after Hardware Reset * bit CONF.SSC must be set to `1' * GPDIR and GPDATA register values must be programmed to the desired I/O function (refer to SSC section) * bit CONF.IOM must be set to `1' IOM(R)-2 operated with double data rate: * special settings of registers MODE1 and MODE2 are necessary: bit fields MODE1.PCM(3:0) must be programmed to 8H bit fields MODE1.TTS(2:0) must be programmed to 0H bit fields MODE1.RTS(2:0) must be programmed to 0H bit fields MODE1.TBS(2:0) must be programmed to 3H bit fields MODE1.RBS(2:0) must be programmed to 5H bit MODE2.RXF must be programmed to `0' bit MODE2.TXR must be programmed to `0' bit MODE2.RSF must be programmed to `0' bit MODE2.TSR must be set to `1' * bit IOMCON1.CLR must be set to `1' bit IOMCON1.ENIH must be set to `1' IOM(R)-2 operated with single data rate: * special settings of registers MODE1 and MODE2 are necessary: bit fields MODE1.PCM(3:0) must be programmed to 8H bit fields MODE1.TTS(2:0) must be programmed to 0H bit fields MODE1.RTS(2:0) must be programmed to 0H bit fields MODE1.TBS(2:0) must be programmed to 4H bit fields MODE1.RBS(2:0) must be programmed to 2H bit MODE2.RXF must be programmed to `0' bit MODE2.TXR must be programmed to `1' bit MODE2.RSF must be programmed to `0' bit MODE2.TSR must be set to `1' * bit IOMCON1.CLR must be set to `0' bit IOMCON1.ENIH must be set to `1' Software Reset For the subfunctions, the states described in Table 17 can also be reached by programming bits (19:17) in PCIRES register (refer to Chapter 5.1.2); i.e., setting those bits to `1' has the same effect for the subfunction as an external RST = low. Resetting the bits to `0' corresponds to deasserting RST for that function.
Subfunction Required Register Programming
IOM(R)-2
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Reset and Initialization Channel Status Channel processing is deactivated. After reset, all buffers are empty and no buffer size is allocated to the channels. The DMA controller state is set to the hold condition. The descriptor and data pointers remain at a random value. On reset, the bits RO and TO are set to `1', whereas RA and TA are set to `0' for all logical channels. All time slots are connected to the logical channel 0 and the following configuration is set: Action Specification LOC = LOOP = LOOPI = 0 Time Slot Assignment fill/mask = 00H, i.e., all bits masked/set to `1' RTI, TTI = 0 channel number = 00H Channel Specification MODE = 00, i.e. TMA FA = 0 IFTF = 0 CRC = 0 INV = 0 TRV = 00, RO = 1 RA = 0 TO = 1 TA = 0 TH = 0 Transmit Descriptor FNUM = 00H, i.e. shared flags in HDLC, only eight zero bits between sent frames for TMB. The E-, S-, X-bits are all set to zero internally by the reset. The receiver is set into the ITF/IDLE state for all channels, i.e. it assumes that on the line there are `1's as interframe time-fill for HDLC.
Data Sheet
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Reset and Initialization General After reset, the valid PCM mode is T1/DS1 x 24-channel 1.536 Mbit/s PCM(3:0) = `0000' in MODE1 register). The value for maximum frame length is `0' (MODE1.MFL). Note that in MUNICH32 (PEB 20320) both values are definied in the action specification.
Data Sheet
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Reset and Initialization
10.2
Initialization
After reset, the MUNICH32X remains in the default state until the host processor generates an action request. The initialization sequence is defined in the action specification. The sequence can be split up into individual procedures for each channel or one procedure to initialize all channels simultaneously. For all procedures, the time slot assignment and the selected channel specifications are loaded into internal MUNICH32X memory. To prevent malfunction, the initialization of the link lists and the allocation of the buffer size to the channels has to be specified before transmission may be initiated. MUNICH32X assumes that timeslot 0 starts on the Rx and Tx lines. They may be resynchronized by 2 rising edges of TSP and RSP, respectively. Before this resynchronization the host should neither remove RO = 1 or TO = 1 nor set LOOP or LOOPI to `1' for any logical channel. During this time any incoming data is ignored, the Tx line is tristated. For each action service the device first reads the control start address in the Control and Configuration Block (CCB), which is pointed to by the contents of the CCBA register. The values of the CCBA register can be changed during operation.
Data Sheet
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Reset and Initialization
Data Sheet
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Slave Register Descriptions
11
11.1
Slave Register Descriptions
Register Set Overview
The following table provides a quick reference to the complete MUNICH32X slave register set. A detailed description of the registers related to each functional block can be found in Chapter 11.2.
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Slave Register Descriptions Note that the PCI Configuration Space Registers are listed in Section 5.1.2. Table 23 MUNICH32X Slave Register Set (BAR1) Read/ Write Offset to PCI BAR1 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H Page
Register Name
MUNICH32X Global Registers Configuration Command Status Status Acknowledge Interrupt Mask Reserved Peripheral Interrupt Queue Length Reserved Serial PCM Core Registers Mode1 Mode2 CC Block Indirect Address Tx Poll Tx Interrupt Queue Base Address Tx Interrupt Queue Length Rx Interrupt Queue Base Address Rx Interrupt Queue Length LBI Registers LBI Configuration LBI CC Block Indirect Address Reserved LBI Start Transfer LBI Tx Interrupt Queue Base Address LBI Tx Interrupt Queue Length LBI Rx Interrupt Queue Base Address LCONF LCCBA - LTRAN LTIQBA LTIQL LRIQBA R/W R/W - W R/W R/W R/W 235 239 239 240 240 241 MODE1 MODE2 CCBA TXPOLL TIQBA TIQL RIQBA RIQL R/W R/W R/W R/W R/W R/W R/W R/W 222 225 227 228 233 233 234 234 CONF CMD STAT STACK IMASK - PIQL - R/W W R W R/W - R/W R/W - 214 217 218 220 221 221 -
Peripheral Interrupt Queue Base Address PIQBA
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Slave Register Descriptions Register Name Read/ Write LRIQL LREG0 LREG1 LREG2 LREG3 LREG4 LREG5 LREG6 LSTAT GPDIR GPDATA GPOD - SSCCON SSCBR SSCTB SSCRB SSCCSE SSCIM - - IOMCON1 IOMCON2 IOMSTAT IOMCIT0 IOMCIT1 IOMCIR0
211
Offset to PCI BAR1 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H 84H 88H 8CH 90H 94H 98H 9CH A0H A4H A8H ACH B0H B4H B8H C0H C4H C8H
Page
LBI Rx Interrupt Queue Length LBI Indirect External Config 0 LBI Indirect External Config 1 LBI Indirect External Config 2 LBI Indirect External Config 3 LBI Indirect External Config 4 LBI Indirect External Config 5 LBI Indirect External Config 6 LBI Status GPP Registers General Purpose Bus Direction General Purpose Bus Data General Purpose Bus Open Drain Reserved SCC Registers SSC Control SSC Baud Rate Generator SSC Tx Buffer SSC Rx Buffer SSC Chip Select Enable SSC Interrupt Mask Register Reserved Reserved IOM(R)-2 Registers IOM(R)-2 Control 1 IOM(R)-2 Control 2 IOM(R) IOM(R) IOM(R) -2 Status -2 C/I Tx Channels 0-3 -2 C/I Rx Channels 0-3
R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W - R/W R/W R/W R R/W R/W - - R/W R/W R R/W R/W R
241 242 242 243 243 244 244 245 248 249 249 250 251 254 255 255 256 257 258 261 263 265 265 266
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IOM(R)-2 C/I Tx Channels 4-7
Data Sheet
PEB 20321 PEF 20321
Slave Register Descriptions Register Name Read/ Write IOMCIR1 IOMTMO IOMRMO - - MBCMD MBDATA1 MBDATA2 MBDATA3 MBDATA4 MBDATA5 MBDATA6 MBDATA7 R R/W R - - R/W R/W R/W R/W R/W R/W R/W R/W Offset to PCI BAR1 CCH D0H D4H D8H DCH E0H E4H E8H ECH F0H F4H F8H FCH Page
IOM(R)-2 C/I Rx Channels 4-7 IOM(R)-2 Tx Monitor IOM(R) -2 Rx Monitor Reserved Reserved Mailbox Registers Mailbox Command Mailbox Data 1 Mailbox Data 2 Mailbox Data 3 Mailbox Data 4 Mailbox Data 5 Mailbox Data 6 Mailbox Data 7
266 267 267 -
Data Sheet
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Slave Register Descriptions Table 24 MUNICH32X Mailbox Registers (LBI Side) Read/ Write Pins LA(2:0) (from LBI side) 0H 1H 2H 3H 4H 5H 6H 7H Page
Register Name
Mailbox Command Mailbox Data 1 Mailbox Data 2 Mailbox Data 3 Mailbox Data 4 Mailbox Data 5 Mailbox Data 6 Mailbox Data 7 Table 25
MBCMD MBDATA1 MBDATA2 MBDATA3 MBDATA4 MBDATA5 MBDATA6 MBDATA7
R/W R/W R/W R/W R/W R/W R/W R/W
MUNICH32X Direct LBI Access (BAR2) Read/ Write PCILBI (XXXX) R/W Offset to PCI BAR2 0000H FFFFH Page
Register Name
PCI Direct LBI Access
Note: Read accesses to unused register addresses always returns the value `0'; the same applies to unused bit fields. An unused register cannot be written to.
Data Sheet
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11.2 11.2.1
Register Bit Field Definitions MUNICH32X Global Registers
This section contains descriptions of all global MUNICH32X slave registers. Configuration Register (CONF) Access Offset Address Reset Value 31 CONF 15 CONF GPIE CST
0 0 0 0 0 0 0
: read/write : 00H : 00000000H 16 0000H 0
CST GPIE SSC LBI IOM LCD(1:0) DBE LBE
General Purpose Bus Interrupt Enable `1': Interrupts on the General Purpose Bus are enabled. Clock Source Timer `0': The clock source is the LBI clock. `1': The clock source is the RSP pin.
SSC
SSC Mode Select `0': These pins provide the high byte of the General Purpose Bus. (refer to Figure 78 on Page 238) `1': The MUNICH32X provides the control functions of the Synchronous Serial Communication (SSC) interface via the pins specified below.
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Slave Register Descriptions Pin No. 100 99 98 97 91 90 89 88 General Purpose Bus Pin GP15 GP14 GP13 GP12 GP11 GP10 GP9 GP8 SSC Mode Function MCLK MTSR MRST not used MCS0 MCS1 MCS2 MCS3
Important Note: Also, if the SSC Mode is selected, the values of General Purpose Bus Direction Register GPDIR(15:8) and General Purpose Bus Open Drain Register GPOD(15:8) must be programmed according to the desired function. LBI LBI Mode Select `0': These pins provide the low byte of the General Purpose Bus. (refer to Figure 78 on Page 238) `1': The MUNICH32X provides the DMA support functions of the Local Bus Interface (LBI) via the pins specified below.
Pin No. 85 84 83 82 81 80 79 78
General Purpose Bus Pin GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
LBI DMA Mode Function DRQTA DRQRA DRQTB DRQRB DACKTA DACKTB DACKRA DACKRB
Note: After reset, the MUNICH32X operates in the General Purpose Bus mode. The General Purpose Bus Direction Register GPDIR allows PCI host software to change the direction of the corresponding pins; after reset, all pins are inputs. The General Purpose Bus Data Register GPDATA is a bi-directional register used for data transfer to/from devices connected to the pins of the General Purpose Bus.
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Slave Register Descriptions IOM LCD IOM(R)-2 Mode Select `1': IOM(R)-2 Mode is selected (only applicable in 2 or 4 Mbit PCM mode) LBI Timer/Clock Division The LBI operating clock is either identical to the PCI Clock, or divided by 2, 4 or 16 according to the following coding: LCD(1:0) 00 01 10 11 LBi Clock Rate PCI Clock PCI Clock devided by 2 PCI Clock devided by 4 PCI Clock devided by 16
DBE
Demux Burst Enable If the DEMUX input pin = `1', this bit field is valid, otherwise it is invalid. In De-multiplexed mode, if DBE is set to `1', the MUNICH32X will perform Master read & write burst of descriptors up to a length of four.
LBE
Little/Big Endian Byte Swap `0': Data will be presented to the PCI bus or de-multiplexed bus in little-endian format for Rx operation, and data is expected in little-endian format for Tx operation. `1': Big endian format is used. Note that this applies only to data, the on-chip registers and the descriptors in CCB in host memory are in little endian format.
Data Sheet
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Slave Register Descriptions Command Register (CMD) Access Offset Address Reset Value : write : 04H : 00000000H 16 TIMV(15:0) 15 CMD TIMV
0 0 0 0 0 0 0 0 0 0 0 TIMR 0 0
31 CMD
0
ARLBI ARPCM
Timer Value A 16-bit value, programmed by host PCI software, which may be loaded into an on-chip down counter (via the TIMR bit field), to provide periodic interrupt generation to the host PCI system. The MUNICH32X generates an interrupt to the host PCI system with a cycle of `TIMV + 2 clock cycles'.
TIMR
Timer Run `0': The timer is stopped. `1': The MUNICH32X loads the value in the TIMV bit fields into the on-chip down counter. The timer runs at the frequency selected in bit field CONF.CST.
ARLBI
Action Request LBI `1': The MUNICH32X will immediately initiate an LBI action request, if no other action request is currently active. Bit is self resetting and will be reset by the LBIF or LBIA interrupt in Status Register STAT.
ARPCM
Action Request Serial PCM Core `1': The MUNICH32X will immediately initiate a serial PCM core action request, if no other action request is currently active. Bit is self resetting and will be reset by the PCMF or PCMA interrupt in Status Register STAT.
Data Sheet
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Slave Register Descriptions Status Register (STAT) Access Offset Address Reset Value : read : 08H : 00000000H 16 0000H 15 STAT 0
31 STAT
PTI PRI LTI LRI IOMI SSCI LBII MBI 0 TI TSPA RSPA LBIF LBIA PCMF PCMA
When an interrupt event occurs, the MUNICH32X sets the flag corresponding to the event. If the interrupt event was non-masked via the Interrupt Mask register IMASK, the MUNICH32X will generate an interrupt to the PCI host system (i.e., it asserts the PCI INTA signal). The host PCI system software may deassert the PCI INTA signal by writing a `1' to the appropriate bit field. PTI Serial PCM Tx Interrupt `1': Indicates the MUNICH32X has written status information into the Tx Interrupt Queue in host memory. PRI Serial PCM Rx Interrupt `1': Indicates the MUNICH32X has written status information into the Rx Interrupt Queue in host memory. LTI LBI Tx Interrupt `1': Indicates the MUNICH32X has written status information into the LBI Tx Interrupt Queue in host memory. LRI LBI Rx Interrupt `1': Indicates the MUNICH32X has written status information into the LBI Rx Interrupt Queue in host memory. IOMI Peripheral IOM(R)-2 Interrupt `1': Indicates the MUNICH32X has written IOM(R)-2 status information into the Peripheral Interrupt Queue in host memory.
Data Sheet
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Slave Register Descriptions SSCI Peripheral SSC interrupt `1': Indicates the MUNICH32X has written SSC status information into the Peripheral Interrupt Queue in host memory. LBII Peripheral LBI Interrupt `1': Indicates the MUNICH32X has written LBI status information into the Peripheral Interrupt Queue in host memory. MBI Peripheral Mailbox interrupt `1': Indicates the MUNICH32X has written Mailbox status information into the Peripheral Interrupt Queue in host memory. TI TSPA Timer Interrupt `1': Indicates the count-down timer has underflowed. PCM TSP Asynchronous `1': PCM frame signal TSP was asynchronous (frame did not match expected clock count) RSPA PCM RSP Asynchronous `1': PCM frame signal RSP was asynchronous (frame did not match expected clock count) LBIF LBIA PCMF PCMA LBI Fail `1': Indicates that LBI action request failed. LBI Acknowledgement `1': Indicates that LBI action request succeeded. Serial PCM Fail `1': Indicates that serial PCM core action request failed. Serial PCM Acknowledgement `1': Indicates that serial PCM action request succeeded. Note: Bit fields (7:0) are standalone interrupt bits, i.e., they have no corresponding interrupt vector queue entry.
Data Sheet
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Slave Register Descriptions Status Acknowledge Register (STACK) Access Offset Address Reset Value : write : 08H : 00000000H 16 0000H 15 STACK 0
31 STACK
PTI PRI LTI LRI IOMI SSCI LBII MBI 0 TI TSPA RSPA LBIF LBIA PCMF PCMA
The PCI host system software may deassert the PCI INTA signal (independent of the IMASK bits) by writing a `1' to the appropriate bit field and hence resetting the corresponding bit field in STAT. Interrupt Mask Register (IMASK) Access Offset Address Reset Value : read/write : 0CH : 0000FF7FH 16 0000H 15 IMASK 0
31 IMASK
PTI PRI LTI LRI IOMI SSCI LBII MBI 0 TI TSPA RSPA LBIF LBIA PCMF PCMA
When set to `1', an event which normally would cause the MUNICH32X to generate an interrupt to the PCI host system will now only trigger the appropriate Status Register bit field (flag) to become set to `1'.
Data Sheet
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Slave Register Descriptions Peripheral Interrupt Queue Base Address Register (PIQBA) Access Offset Address Reset Value : write/read : 14H : 00000000H 16 PIQBA(31:16) 15 PIQBA PIQBA(15:2) 0 0 0
31 PIQBA
Specifies the host memory Peripheral Interrupt Queue base or start address; this address must be DWORD-aligned. Peripheral Interrupt Queue Length Register (PIQL) Access Offset Address Reset Value : read/write : 18H : 00000000H 16 0000H 15 PIQL 0 0 0 0 0 0 0 0 PIQL (7:0) 0
31 PIQL
Specifies the length of the Peripheral Interrupt Queue in number of DWORDs: Interrupt Queue length = 4 x PIQL (DWORDs). The maximum length of 1024 DWORDs is achieved by setting PIQL(7:0) = 00H.
Data Sheet
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11.2.2
Serial PCM Core Registers
This section contains descriptions of all serial PCM core slave registers. Mode1 Register (MODE1) Access Offset Address Reset Value 31 MODE1 15 MODE1 REN RID MFLD PCM PCM Transmission Rate Specifies the PCM transmission rate used by the Serial PCM core as indicated in the table below: Bit 31 0 0 0 0 1 1 1 Bit 30 0 1 1 1 0 0 0 Bit 29 0 0 0 1 0 0 1 Bit 28 0 0 1 0 0 1 0 PCM Data Rate 1.536 Mbit/s 1.544 Mbit/s 3.088 Mbit/s 6.176 Mbit/s 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s MFL(12:0) PCM(3:0) TTS(2:0) TBS(2:0) RTS(2:0) : read/write : 20H : 00000000H 16 RBS(2:0) 0
Note: All other values are illegal and will produce undefined results. TBS/RBS Tx/Rx Bit Shift Specifies the position of the Tx/Rx bits relative to the synch. pulses in transmit and receive direction. Important note: In order to be compatible to the MUNICH32 (i.e., no bit shift), these bit fields must be programmed to `4'.
Data Sheet
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Slave Register Descriptions Bit 24 Bit 23 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Bit 22 0 1 0 1 0 1 0 1 Shift of Tx Bit Bit relative to Tx Sync 18 Pulse -4 -3 -2 -1 0 1 2 3 0 0 0 0 1 1 1 1 Bit 17 0 0 1 1 0 0 1 1 Bit 16 0 1 0 1 0 1 0 1 Shift of Rx Bit relative to Rx Sync Pulse -4 -3 -2 -1 0 1 2 3
Note: To be consistent with the MUNICH32, PEB 20320, TBS(2:0) and RBS(2:0) must be programmed to `4'. TTS/RTS Tx/Rx Time Slot The MUNICH32X uses only valid timeslots according to the following table (n = 0 ... 31; k = 1 in 2-Mbit mode, k = 2 in 4-Mbit mode; k = 4 in 8-Mbit mode n = 0 ... 23; k = 1 in 1.5-Mbit mode, k = 2 in 3-Mbit mode, k = 4 in 6-Mbit mode): Bit 27 0 0 0 0 1 1 1 1 Bit 26 0 0 1 1 0 0 1 1 Bit 25 0 1 0 1 0 1 0 1 Valid Timeslots Transmit kxn (k x n) + 1 (k x n) + 2 (k x n) + 3 reserved reserved reserved reserved Bit 21 0 0 0 0 1 1 1 1 Bit 20 0 0 1 1 0 0 1 1 Bit 19 0 1 0 1 0 1 0 1 Valid Timeslots Receive kxn (k x n) + 1 (k x n) + 2 (k x n) + 3 reserved reserved reserved reserved
Note: In 3-Mbit or 4-Mbit PCM mode, only the first 2 options (bit fields 21, 20, 27 and 26 equal to `0') are valid. In 6-Mbit or 8-Mbit PCM mode, all 4 options are valid.
Data Sheet
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Slave Register Descriptions REN Rx Enable `0': Serial PCM core Rx operation is disabled. `1': Serial PCM core Rx operation is enabled. RID Rx Interrupt Disable `0': A serial PCM Rx interrupt event will cause the MUNICH32X to generate an interrupt to the host PCI system, if the event was non-masked via the Interrupt Mask Register. `1': A serial PCM Rx interrupt event will not cause the MUNICH32X to generate an interrupt to the host PCI system. MFLD Maximum frame Length Check Disabled `0': The MFL check is enabled. `1': The MFL check is disabled. MFL Maximum Frame Length Maximum size of a received frame in HDLC, TMB and TMR mode (up to 8192 bytes). A received frame is aborted and an interrupt is generated if the size of a received frame exceeds the MFL value. MFL applies to all channels.
Data Sheet
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Slave Register Descriptions MODE2 Register (MODE2) Access Offset Address Reset Value 31 MODE2 15 MODE2 HPOLL 0 0 0 0 0 0 0000H 0 0 HPOLLSPOLLLSIM REIM TEIM RXF TXR RSF TSR : read/write : 24H : 00000000H 16
Hold Poll The MODE2.HPOLL bit field provides capability for the MUNICH32X to be configured for Tx polling identical to that of the MUNICH32. In this case (i.e. HPOLL = `1' & TXPOLL(31:0) = 00000000H), the MUNICH32X checks the status of the the TxHOLD bit field for each time slot assigned to the particular channel. When the TxHold bit field is reset, the MUNICH32X immediately resumes transmission (see TXPOLL register).
SPOLL
Slow Poll The MODE2.SPOLL bit field (slow poll) provides capability for the MUNICH32X to be configured for a Tx poll rate determined by the Tx synchronization pulses divided by 8 (125 s x 8 = 1 ms). In this case (i.e. SPOLL = `1' & TXPOLL.POLL(31:0) = FFFFFFFFH), Tx polling per channel is performed every 8th PCM frame with four groups of interleaved DMA channels, as shown below: Frame 0 1 n 7 DMA channels 0, 8, 16, 24 1, 9, 17, 25 n, n + 8, n + 16, n + 24 7, 15, 23, 31 (see TXPOLL register).
Note: It is recommended not to use the Slow Poll option in combination with Sub Channeling on any one or more channels (for description of Sub Channeling refer to Chapter 12.5).
Data Sheet
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Slave Register Descriptions LSIM Late Stop Interrupt Mask `1': A Late Stop event (refer to serial PCM core interrupt vector description) will not cause the MUNICH32X to generate an interrupt to the host PCI system. REIM Rsync Error Interrupt Mask `1': An Rsync error condition will not cause the MUNICH32X to generate an interrupt to the host PCI system. TEIM Tsync Error Interrupt Mask `1': An Tsync error condition will not cause the MUNICH32X to generate an interrupt to the host PCI system. RXF Rx Data Falling Edge `0': RXD is sampled on the rising edge of RXCLK. `1': RXD is sampled on the falling edge of RXCLK. TXR Tx Data Rising Edge `0': TXD is updated on the falling edge of TXCLK. `1': TXD is updated on the rising edge of TXCLK. RSF RSP Falling Edge `0': RSP is sampled on the rising edge of RXCLK. `1': RSP is sampled on the falling edge of RXCLK. TSR TSP Rising Edge Note: In previous versions of the User's Manual this bit was incorrectly named TSF. `0': TSP is sampled on the falling edge of TXCLK. `1': TSP is sampled on the rising edge of TXCLK.
Data Sheet
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Slave Register Descriptions CC Block Indirect Address Register (CCBA) Access Offset Address Reset Value 31 CCBA 15 CCBA CCBA(15:2) 0 CCBA(31:16) 0 0 : read/write : 28H : 00000000H 16
The CC Block Indirect Address Register points to the location in host memory which contains the actual base address pointer to the Control and Configuration Block (for serial PCM core DMA). This address must be DWORD-aligned.
Data Sheet
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Slave Register Descriptions Tx Poll Register (TXPOLL) Access Offset Address Reset Value 31 TXPOLL 15 TXPOLL POLL(15:0) POLL(31:16) 0 : read/write : 2CH : 00000000H 16
The Tx Poll Register provides an asserted low POLLn bit field per Serial PCM core channel that allows host software to configure the MUNICH32X to respond in one of three ways to a Tx idle condition, depending upon the state of the TXPOLL.POLLn bit field (additionally, the states of the MODE2.SPOLL and MODE2.HPOLL bit fields are evaluated in the Tx polling process). The flow diagram in Figure 76 illustrates the Tx polling process. 1. Most applications will set the Tx HOLD bit field in Tx descriptor and have both the MODE2.SPOLL bit field and the MODE2.HPOLL bit field equal to zero. With this configuration, the MUNICH32X will disable polling either immediately or after one poll (depending upon the state of the TXPOLL.POLLn bit field). If TXPOLL.POLLn = 1, Tx polling stops immediately, while if TXPOLL.POLLn = 0, a single poll is performed. Software may enable a single poll for a particular channel by resetting the appropriate TXPOLL.POLLn bit field. With this technique, bus utilization of idle channels is very low, and startup from a temporary idle state is resumed after a simple write operation to the MUNICH32X's TXPOLL register. 2. If both the TXPOLL.POLLn bit field and the MODE2.SPOLL bit field are set, and the MUNICH32X detects the Tx HOLD bit field set for that particular channel, then the MUNICH32X will perform polling for all channels at a rate controlled by the Tx synch pulses divided-by-8. Operation of this mode is described in detail in the SPOLL (slow poll) section of the MODE2 Register. 3. If the TXPOLL.POLLn bit field is reset, while the MODE2.HPOLL bit field is set, and the MUNICH32X detects the Tx HOLD bit field set for that particular channel, then the MUNICH32X will perform Tx polling identical to that of the MUNICH32 (PEB 20320) for that particular channel. In this case, the MUNICH32X checks the status of the Tx HOLD bit field for each time slot assigned to this channel. In this way, if the bit has been cleared, the MUNICH32X will immediately resume transmission. Although this method is simpler (in concept) for the software design, it causes the MUNICH32X to consume higher than normal bus bandwidth. For this reason, this is the least desirable
Data Sheet
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Slave Register Descriptions of the methods. Operation of this mode is described in detail in the HPOLL section of the MODE2 register.
Normal Operation: No A Tx HOLD=1? The MUNICH32X reads data from the buffer pointed to by the Tx descriptor
Yes
No TXPOLL.POLLn=0?
For that channel polling stops immediately. to (B)
Yes
Yes MODE2.HPOLL=1?
For that channel the MUNICH32X polls using the MUNICH32 method.
No For that channel, the MUNICH32x sets the TXPOLL.POLLn bit field to 1. (next page)
Data Sheet
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(from previous page) At the next time slot for that channel, the MUNICH32X reads the first two DWORDs of that Tx descriptor (again) and checks the value of the Tx HOLD bit field.
Tx HOLD=1?
NO
For that channel, normal operation resumes.
YES For that channel, polling stops immediately.
YES MODE2.SPOLL=1?
For all channels the MUNICH32X polls at a rate controlled by the Tx sync pulses divided by 8.
NO When data is ready, host software resets the Tx HOLD bit field in the Tx descriptor to 0 and then resets the TXPOLL.POLLn bit field to 0.
(to A)
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(B)
MODE2.SPOLL=1?
YES
For all channels, the MUNICH32X polls at a rate controlled by the Tx sync pulses divided by 8.
NO When data is ready, host software resets the Tx HOLD bit field in the Tx descriptor to 0 and then resets the TXPOLL.POLLn bit field to 0.
(to A) Figure 76 Tx Polling Procedure
Data Sheet
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Slave Register Descriptions Interupt Queue Registers The MUNICH32X provides data status information (of the serial PCM core and the LBI peripheral) to the host PCI system via dedicated Rx and Tx Interrupt Queues in host memory, which have the same structure as shown in Figure 77. Non-data status information is provided via the serial PCM core Status Register STAT and the LBI status register LSTAT.
overwrite START ADDRESS (Interrupt Queue Address) interrupt information DWORD 1 interrupt information DWORD 2 interrupt information DWORD 3 length = (n + 1) x 16 DWORD (n = 0...255) min. size: 16 DWORD max. size: 4096 DWORD ('n' is defined in registers PIQL, TIQL, RIQL, LTIQL, LRIQL)
interrupt information DWORD (n + 1) x 16
ITD10365
Figure 77
Interrupt Queue Structure
For each interrupt event, the MUNICH32X writes status information into the appropriate interrupt queue, increments the pointer to the next address in this block and generates an interrupt to the host PCI system, if non-masked. It is the responsibility of the host PCI software to read the status information out of the appropriate interrupt queue. When the MUNICH32X arrives at the end of an interrupt queue, it will jump to the start address of that interrupt block again and overwrite the previous information. If the start address or the length of a queue is changed during operation, an action request with the `IA' bit set has to be initiated.
Data Sheet
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Slave Register Descriptions Tx Interrupt Queue Base Address (TIQBA) Access Offset Address Reset Value : read/write : 30H : 00000000H 16 TIQBA(31:16) 15 TIQBA TIQBA(15:2) 0 0 0
31 TIQBA
Specifies the host memory serial PCM core Tx Interrupt Queue base or start address; this address must be DWORD-aligned. Tx Interrupt Queue Length (TIQL) Access Address relative to BAR1 Reset Value : read/write : 34H : 00000000H 16 0000H 15 TIQL 0 0 0 0 0 0 0 0 TIQL(7:0) 0
31 TIQL
Specifies the DWORD count of the serial PCM core Tx Interrupt Queue in host memory. The maximum size of the Queue is 4096 DWORDs ((n + 1) x 16 DWORDs, where n = TIQL(7:0); refer to Figure 77).
Data Sheet
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Slave Register Descriptions Rx Interrupt Queue Base Address (RIQBA) Access Offset Address Reset Value : read/write : 38H : 00000000H
31 RIQBA 15 RIQBA RIQBA(15:2) 0 RIQBA(31:16)
16
0 0
Specifies the host memory serial PCM core Rx Interrupt Queue base or start address; this address must be DWORD-aligned. Rx Interrupt Queue Length (RIQL) Access Offset Address Reset Value : read/write : 3CH : 00000000H 16 0000H 15 RIQL 0 0 0 0 0 0 0 0 RIQL(7:0) 0
31 RIQL
Specifies the DWORD count of the serial PCM core Rx Interrupt Queue in host memory. The maximum size of the Queue is 4096 DWORDs ((n + 1) x 16 DWORDs, where n = RIQL(7:0); refer to Figure 77).
Data Sheet
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Slave Register Descriptions
11.2.3
LBI Registers
This section contains descriptions of all LBI registers. LBI Configuration Register (LCONF) Access: Offset address: Reset Value: 31 LCONF
IPA DCA DCB MDA MDB SDA DID CDP 0
read/write 40H 00600000H 16
EBCRES LBIRES DV(2:0) 0 0
15 LCONF MCTC
0 0 0
0
HE1 HE2 SPINT EALE HDEN BTYP(1:0) RDEN ABM MCTC(3:0)
Memory Cycle Time Control (Number of memory cycle time wait states) 0 0 0 0: 15 waitstates (Number = 15 - ) ... 1 1 1 1: No waitstates
BTYP
External Bus Configuration 0 0: 8-bit De-multiplexed Bus 0 1: 8-bit Multiplexed Bus 1 0: 16-bit De-multiplexed Bus 1 1: 16-bit Multiplexed Bus
RDEN
LRDY Input Enable `0': External bus cycle is controlled by bit field MCTC only `1': External bus cycle is controlled by the bit field MCTC and signal LRDY
HDEN
HOLD Enable `0': Bus arbitration ignored `1': LBI bus arbitration using LHOLD, LHLDA, LBREQ enabled
EALE
Extended ALE `0': Single LBI clock ALE pulse width `1': 1.5 LBI clocks ALE pulse width
Data Sheet
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Slave Register Descriptions CDP Combined DMA Pins (valid only if CONF.LBI = `1') `0': DMA Acknowledge pins are separated `1': DMA Acknowledge pins are combined, i.e. DACKTA & DACKRA become DACKA, and DACKTB & DACKRB become DACKB. In this case, the pin LCLKOUT1 (EBC system clock phase 1 output), as well as the pin PHI1 (additional PCI clock phase 1 output) is available, if the direction of the pins has been programmed to output by setting the bit fields GPDIR.0 and GPDIR.1 to `1' (see Figure 78 (b)). ABM Arbitration Master Function `0': MUNICH32X is arbitration slave device (LHLDA pin is input) `1': MUNICH32X is arbitration master device (LHLDA pin is output) LBIRES Reset LBI DMSM Block `0': Resets and keeps the DMSM in its initial state (same as hardware reset). `1': Normal DMSM operation. EBCRES Reset LBI EBC Block `0': Resets and keeps the External Bus Controller in its initial state (same as hardware reset). `1': Normal EBC operation. DCA Disregard the Interrupts for Channel A `0': Normal DMSM operation regarding interrupt processing `1': DMSM passes all Channel A interrupts to interrupt queue (including RPF, XPR, RMC) DCB Disregard the Interrupts for Channel B `0': Normal DMSM operation regarding interrupt processing `1': DMSM passes all Channel B interrupts to interrupt queue (including RPF, XPR, RMC)
Data Sheet
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Slave Register Descriptions MDA Mode Channel A `0': Interrupt mode `1': DMA assisted mode MDB Mode Channel B `0': Interrupt mode `1': DMA assisted mode SDA Shared DMA Channel A `0': Separate Tx and Rx DMA (default) `1': Shared Tx and Rx signals. Requests on DRQTA (for both Tx and Rx), and Acknowldege on DACKA (for both Tx and Rx). DID Direction of DMA signals (Valid only if SDA = 1) `0': DMA request for Rx direction (from LBI peripheral) `1': DMA request for Tx direction (from LBI peripheral) HE1 HSCX/ESCC Register Decoding on Pin LINTI1 `0': ESCC2 register decoding LINTI1 input signal polarity active high `1': HSCX register decoding LINTI1 input signal polarity active low HE2 HSCX/ESCC Register Decoding on Pin LINTI2 `0': ESCC2 register decoding LINTI2 input signal polarity active high `1': HSCX register decoding LINTI2 input signal polarity active low SPINT Separate Interrupt Pins `0': LINTI1 pin is used for both DMA channels; LINTI2 pin is disabled `1': LINTI1 pin is used for DMA channel A, LINTI2 pin is used for DMA channel B; LINTI2 pin is enabled
Data Sheet
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Slave Register Descriptions DV DMA Request Validation Period 0 0 0: No delay 1 0 0: reserved 1 0 1: Validate DRQTA & DRQTB for 8 LCLKOUT periods (falling edge) 1 1 0: Validate DRQTA & DRQTB for 16 LCLKOUT periods (falling edge) 1 1 1: Validate DRQTA & DRQTB for 32 LCLKOUT periods (falling edge) The DMA request is considered in-active only after the programmed delay. This is used to determine the end of packet indication. IPA Interrupt Pass This bit field is necessary when connecting a FALC54 (PEB 2254) to the LBI. `0': All interrupts are interpreted by the Data Mode State Machine (DMSM). `1': Interrupts related to registers ISR2, ISR3 of FALC54 are not interpreted by the DMSM, but passed to the LBI interrupt queue. Note: Any change to register LCONF settings must be followed by an EBC and LBI reset to ensure proper operation based on the new settings. This can be achieved by writing `0' to bits EBCRES and LBIRES with any write access which changes any settings and set these bits to `1' again with a second write access to register LCONF.
General Purpose Bus I/O Alternate Function a) Alternate Function b)
GP15 GP14 GP13 GP12 GP11 GP10 GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
CONF.SSC = 0
MCLK MTSR MRST N.C. MCS0 MCS1 MCS2 MCS3 DRQTA DRQRA DRQTB DRQRB DACKTA DACKTB DACKRA DACKRB
CONF.SSC = 1
CONF.LBI = 0
CONF.LBI = 1
DRQTA DRQRA DRQTB DRQRB DACKA DACKB LCLKOUT1* PHI1*
CONF.LBI = 1, LCONF.CDP = 1 * requires GPDIR = 1
ITB10366
Figure 78
General Purpose Bus I/O and Alternate LBI/SSC Functions
Data Sheet
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Slave Register Descriptions LBI CC Block Indirect Address Register (LCCBA) Access Offset Address Reset Value : read/write : 44H : 00000000H 16 LCCBA(31:16) 15 LCCBA LCCBA(15:2) 0 0 0
31 LCCBA
The LBI CC Block Indirect Address Register points to the location in host memory which contains the actual base address pointer to the Control and Configuration Block (for LBI DMAC). This address must be DWORD-aligned. LBI Start Transfer Register (LTRAN) Access Offset Address Reset Value : read/write : 4CH : 00000003H 16 0000H 15 LTRAN GOB
0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 LTRAN
0
GOB GOA
LBI Start Transfer Channel B `0': Valid data in Next Tx Descriptor address is transferred on LBI channel B, if Tx HOLD for channel B is not set.
GOA
LBI Start Transfer Channel A `0': Valid data in Next Tx Descriptor address is transferred on LBI channel A, if Tx HOLD for channel A is not set.
Data Sheet
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Slave Register Descriptions LBI Tx Interrupt Queue Base Address Register (LTIQBA) Access Offset Address Reset Value : read/write : 50H : 00000000H 16 LTIQBA(31:16) 15 LTIQBA LTIQBA(15:2) 0 0 0
31 LTIQBA
Specifies the host memory LBI DMAC Tx Interrupt Queue base or start address; this address must be DWORD-aligned. LBI Tx Interrupt Queue Length Register (LTIQL) Access Offset Address Reset Value : read/write : 54H : 00000000H 16 0000H 15 LTIQL 0 0 0 0 0 0 0 0 LTIQL(7:0) 0
31 LTIQL
Specifies the DWORD count of the LBI DMA Controller Tx Interrupt Queue in host memory. The maximum size of the Queue is 4096 DWORDs ((n + 1) x 16 DWORDs, where n = LTIQL(7:0); refer to Figure 77).
Data Sheet
240
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Slave Register Descriptions LBI Rx Interrupt Queue Base Address Register (LRIQBA) Access Offset Address Reset Value : read/write : 58H : 00000000H 16 LRIQBA(31:16) 15 LRIQBA LRIQBA(15:2) 0 0 0
31 LRIQBA
Specifies the host memory LBI DMAC Rx Interrupt Queue base or start address; this address must be DWORD-aligned. LBI Rx Interrupt Queue Length Register (LRIQL) Access Offset Address Reset Value : read/write : 5CH : 00000000H 16 0000H 15 LRIQL 0 0 0 0 0 0 0 0 LRIQL(7:0) 0
31 LRIQL
Specifies the DWORD count of the LBI Rx Interrupt Queue in host memory. The maximum size of the Queue is 4096 DWORDs ((n + 1) x 16 DWORDs, where n = LRIQL(7:0); refer to Figure 77).
Data Sheet
241
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Slave Register Descriptions LBI Indirect External Configuration Register 0 (LREG0) Access Offset Address Reset Value : read/write : 60H : 00000000H 16 OFFSETA(7:0) 15 LREG0 CMDRA(7:0) STARA(7:0) FIFOA(7:0) 0
31 LREG0
Provides indirect pointers to the appropriate register of the LBI peripheral, e.g., Siemens ESCCx, HSCX or FALC54 devices. For example, the required LREG0 value to be programmed for ESCC2 operation is 00002020H. Note that the complete table of LREG0 ... LREG5 settings for connecting other peripherals is shown after the LREG6 description. LBI Indirect External Configuration Register 1 (LREG1) Access Offset Address Reset Value : read/write : 64H : 00000000H 16 GISA(7:0) 15 LREG1 ISR1A(7:0) RBCLA(7:0) ISR0A(7:0) 0
31 LREG1
Provides indirect pointers to the appropriate register of the LBI peripheral, e.g., Siemens ESCCx, HSCX or FALC54 devices. For example, the required LREG1 value to be programmed for ESCC2 operation is 383A3B2AH.
Data Sheet
242
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Slave Register Descriptions LBI Indirect External Configuration Register 2 (LREG2) Access Offset Address Reset Value : read/write : 68H : 00000000H 16 OFFSETB(7:0) 15 LREG2 CMDRB(7:0) STARB(7:0) FIFOB(7:0) 0
31 LREG2
Provides indirect pointers to the appropriate register of the LBI peripheral, e.g., Siemens ESCCx, HSCX or FALC54 devices. For example, the required LREG2 value to be programmed for ESCC2 operation is 00406060H. LBI Indirect External Configuration Register 3 (LREG3) Access Offset Address Reset Value : read/write : 6CH : 00000000H 16 GISB(7:0) 15 LREG3 ISR1B(7:0) RBCLB(7:0) ISR0B(7:0) 0
31 LREG3
Provides indirect pointers to the appropriate register of the LBI peripheral, e.g., Siemens ESCCx, HSCX or FALC54 devices. For example, the required LREG3 value to be programmed for ESCC2 operation is 387A7B6AH.
Data Sheet
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Slave Register Descriptions LBI Indirect External Configuration Register 4 (LREG4) Access Offset Address Reset Value : read/write : 70H : 00000000H 16 OFFSETC(7:0) 15 LREG4 OFFSETD(7:0) FIFOD(7:0) FIFOC(7:0) 0
31 LREG4
Provides indirect pointers to the appropriate register of the LBI peripheral, e.g., Siemens ESCCx, HSCX or FALC54 devices. For example, the required LREG4 value to be programmed for ESCC2 operation is 00000040H. LBI Indirect External Configuration Register 5 (LREG5) Access Offset Address Reset Value : read/write : 74H : 00000000H 16 0 RMC(2:0) XTF/XHF(2:0) XME(2:0) 0 0 0 0 0 0 ICA/EXI(2:0) CEC(2:0) RPF(2:0) RME(2:0) XPR(2:0)
31 LREG5 0 15 LREG5 0
Provides indirect pointers to the appropriate register bit fields of the LBI peripheral, e.g., Siemens ESCCx, HSCX or FALC54 devices. For example, the required LREG5 value to be programmed for ESCC2 operation is 3B200438H. Note: The register bit fields XTF/XHF and ICA/EXI are not used in all LBI peripherals.
Data Sheet
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Slave Register Descriptions LBI Indirect External Configuration Register 6 (LREG6) Access Offset Address Reset Value : read/write : 78H : 00000000H 16
0 RFTB(5:0) 0 0 RFTA(5:0)
31 LREG6
0
15 LREG6 RFTB/ RFTA
0000H
0
MB MXB MRMB MRPB MA MXA MRMA MRPA
RFIFO Threshold Level Channel B/A Controls the sizes of the accessible part of RFIFO of the LBI peripheral, e.g., Siemens ESCCx or FALC devices. Valid values are: 20H: Size = 32 bytes, 10H: Size = 16 bytes, 4H: Size = 4 bytes, 2H: Size = 2 bytes. The value to be programmed depends on the corresponding register value of the peripheral (ESCC2: CCR4 register, FALC54: CCR1 register). Note that for connection of HSCX on LBI, the value must be set to 32H.
MB MXB MRMB MRPB MA MXA
Mask All Channel B `1': All interrupts on LBI channel B are masked. Mask XPR Channel B `1': XPR interrupts on LBI channel B are masked. Mask RME Channel B `1': RME interrupts on LBI channel B are masked. Mask RPF Channel B `1': RPF interrupts on LBI channel B are masked. Mask All Channel A `1': All interrupts on LBI channel A are masked. Mask XPR Channel A `1': XPR interrupts on LBI channel A are masked.
Data Sheet
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Slave Register Descriptions MRMA MRPA Mask RME Channel A `1': RME interrupts on LBI channel A are masked. Mask RPF Channel A `1': RPF interrupts on LBI channel A are masked. Examples of DMSM register values for inter-acting with different external peripherals that may be connected to the LBI and may be supported for automated data transfer using the DMSM are shown in the following tables (LREG6 is not considered since its value changes depending on the external interrupt bit fields that need to be masked): Table 26 LREG0 LREG1 LREG2 LREG3 LREG4 LREG5 LBI External Configuration for ESCC2 Byte3 00H 38H 00H 38H 00H Byte 2 00H 3AH 40H 7AH 00H Byte1 20H 3BH 60H 7BH 00H Byte 0 20H 2AH 60H 6AH 40H
Register Name
RMC(111B), XTF(011B), XME(001B)
RPF(000B), RME(111B), XPR (000B), CEC(010B), ICA(000B)
Note: For Interrupt channel A mode use offset A & FIFOA pointers, and for Interrupt channel B mode use offset B & FIFOB pointers. For DMA A assisted transfers use offset C & FIFOC pointers, and for DMA B assisted transfers use offset D & FIFOD pointers in DMSM registers.
Data Sheet
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Slave Register Descriptions Table 27 LBI External Configuration for HSCX Byte3 00H 60H 00H 60H 00H Byte 2 00H 20H 40H 60H 00H Byte1 21H 00H 61H 00H 00H Byte 0 21H 25H 61H 65H 40H
Register Name LREG0 LREG1 LREG2 LREG3 LREG4 LREG5
RMC(111B), XTF(011B), XME(001B)
RPF(110B), RME(111B), XPR (100B), CEC(010B), ICA(010B)
Note: When a HSCX is connected to the LBI, the packet size in DMA mode must be a multiple of 32 bytes. Table 28 LREG0 LREG1 LREG2 LREG3 LREG4 LREG5 LBI External Configuration for FALC54 (HDLC mode) Byte3 00H 6EH 00H 6EH 00H Byte 2 00H 6AH 00H 68H 00H Byte1 02H 6BH 02H 69H 00H Byte 0 64H 66H 64H 66H 00H
Register Name
RMC(111B), XHF(011B), XME(001B)
RPF(000B), RME(111B), XPR (000B), CEC(010B), ICA(000B)
Note: When a FALC54 is connected to the LBI, only the LBI channel `B' is used for data transfer. In this case, the interrupt mask bit fields for channel A (refer to LREG6 register description) are not valid.
Data Sheet
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Slave Register Descriptions LBI Status Register (LSTAT) Access: Offset address: Reset Value: 31 LSTAT 15 LSTAT HLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H 0 INT2 INT1 HLD read 7CH 00000000H 16
EBC HOLD Indicator Indicates EBC status `0': The EBC is currently driving the bus. `1': The EBC is currently in HOLD mode.
INT1 INT2
EBC LINTI1 Indicator Indicates LINTI1 as interrupt source. EBC LINTI2 Indicator Indicates LINTI2 as interrupt source.
Data Sheet
248
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Slave Register Descriptions
11.2.4
GPP Registers
General Purpose Bus Directon Register (GPDIR) Access Offset Address Reset Value 31 GPDIR 15 GPDIR GPDIR GPDIR(15:0) General Purpose Bus Directon `0': General Purpose Bus GP0 ... GP15 pins are input pins `1': General Purpose Bus pins GP0 ... GP15 are output pins General Purpose Bus Data Register (GPDATA) Access Offset Address Reset Value : read/write : 84H : 00000000H 16 0000H 15 GPDATA GPDATA(15:0) 0 0000H 0 : read/write : 80H : 00000000H 16
31 GPDATA
16 bit data register for the General Purpose Bus.
Data Sheet
249
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Slave Register Descriptions General Purpose Bus Open Drain Register (GPOD) Access Offset Address Reset Value : read/write : 88H : 00000000H 16 0000H 15 GPOD GPOD GPOD(15:0) General Purpose Bus Open Drain `1': Corresponding General Purpose Bus pins GP0 ... GP15 are open-drain pins 0
31 GPOD
Data Sheet
250
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Slave Register Descriptions
11.2.5
SSC Registers
This section contains descriptions of all SSC slave registers. SSC Control Register (SSCCON) a) Programming Mode (SSCEN = `0') Access Offset Address Reset Value : read/write : 90H : 00000000H 16 0000H 15 SSCCON SSC SSC 0
EN MS 0 SSC SSC SSC SSC BEN PEN REN TEN 0 SSC SSC SSC PO PH HB SSCBM(3:0)
31 SSCCON
0
SSCBM
SSC Data Width Selection 0H: Reserved. Do not use this combination. 1 ... 15H: Transfer Data Width is 2 ... 16 bit (+1)
SSCHB
SSC Heading Control Bit `0': Transmit/Receive LSB First `1': Transmit/Receive MSB First
SSCPH
SSC Clock Phase Control Bit `0': Shift transmit data on the leading clock edge, latch on trailing edge `1': Latch receive data on leading clock edge, shift on trailing edge
SSCPO
SSC Clock Polarity Control Bit `0': Idle clock line is low, leading clock edge is low-to-high transition `1': Idle clock line is high, leading clock edge is high-to-low transition
SSCTEN
SSC Transmit Error Enable Bit `0': Ignore transmit errors `1': Check transmit errors
SSCREN
SSC Receive Error Enable Bit `0': Ignore receive errors `1': Check receive errors
Data Sheet
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Slave Register Descriptions SSCPEN SSC Phase Error Enable Bit `0': Ignore phase errors `1': Check phase errors SSCBEN SSC Baudrate Error Enable Bit `0': Ignore baudrate errors `1': Check baudrate errors SSCMS SSC Master Select Bit `0': Slave Mode. Operate on shift clock received via MCLK. `1': Master Mode. Generate shift clock and output it via MCLK. SSCEN SSC Enable Bit = `0' Transmission and reception disabled. Access to control bits. b) Operating Mode (SSCEN = `1') Access Offset Address Reset Value : read/write : 90H : 00000000H 16 0000H 15 SSCCON SSC SSC 0 SSC SSC SSC SSC SSC 0
EN MS BSY BE PE RE TE 0 0 0 SSCBC(3:0)
31 SSCCON
0
Data Sheet
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Slave Register Descriptions SSCBC SSCTE SSCRE SSCPE SSCBE SSC Bit Count Field Shift counter is updated with every shifted bit. Do not write to! SSC Transmit Error Flag `1': Transfer starts with the slave's transmit buffer not being updated SSC Receive Error Flag `1': Reception completed before the receive buffer was read SSC Phase Error Flag `1': Received data changes around sampling clock edge SSC Baudrate Error Flag `1': More than factor 2 or 0.5 between Slave's actual and expected baudrate SSCBSY SSCMS SSC Busy Flag Set while a transfer is in progress. Do not write to! SSC Master Select Bit `0': Slave Mode. Operate on shift clock received via MCLK. `1': Master Mode. Generate shift clock and output it via MCLK. SSCEN SSC Enable Bit = `1' Transmission and reception enabled. Access to status flags and Master/Slave control.
Data Sheet
253
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Slave Register Descriptions SSC Baud Rate Generator Register (SSCBR) Access Offset Address Reset Value : read/write : 94H : 00000000H 16 0000H 15 SSCBR SSCBR(15:0) 0
31 SSCBR
These bits define the baud rate used for data transfer via the SSC interface. Reading SSCBR (while SSC in enabled) returns the timer value. Reading SSCBR (while SSC in disabled) returns the programmed reload value. The desired reload value of the baud rate can be written to SSCBR when the SSC interface is disabled. The table below lists some possible baud rates together with the required reload values, assuming a PCI clock of 20 MHz (33 MHz also supported). SSCBR(15:0) 0000H 0001H 0002H 0003H 0004H 0009H 0063H 03E7H 270FH FFFFH Baud Rate Reserved. Use a reload value > 0. 5 MBaud 3.3 MBaud 2.5 MBaud 2.0 MBaud 1.0 MBaud 100 KBaud 10 KBaud 1.0 KBaud 152.6 Baud Bit Time - 200 ns 300 ns 400 ns 500 ns 1 s 10 s 100 s 1 ms 6.6 ms
Note 1: The contents of SSCBR must always be > 0. Note 2: Never write to SSCBR, while the SSC is enabled.
Data Sheet
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Slave Register Descriptions SSC Tx Buffer Register (SSCTB) Access Offset Address Reset Value : write : 98H : 00000000H 16 0000H 15 SSCTB SSCTB(15:0) 0
31 SSCTB
Contains the last of the SSC interface transmitted 16-bit word. SSC Rx Buffer Register (SSCRB) Access Offset Address Reset Value 31 SSCRB 15 SSCRB SSCRB(15:0) 0000H 0 : write : 9CH : 00000000H 16
Contains the last of the SSC interface received 16-bit word.
Data Sheet
255
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Slave Register Descriptions SSC Chip Select Enable Register (SSCCSE) Access Offset Address Reset Value : read/write : A0H : 00000000H 16 0000H 15 SSCCSE AS3
0 0 0 0 0 0 0 0 AS3 AS2 AS1 AS0 0 0 0
31 SSCCSE
0
0
Pin MCS3 Control `0': Activation of MCS3 chip select pin `1': Hardware automatically controls MCS3
AS2
Pin MCS2 Control `0': Activation of MCS2 chip select pin `1': Hardware automatically controls MCS2
AS1
Pin MCS1 Control `0': Activation of MCS1 chip select pin `1': Hardware automatically controls MCS1
AS0
Pin MCS0 Control `0': Activation of MCS0 chip select pin `1': Hardware automatically controls MCS0
Data Sheet
256
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Slave Register Descriptions SSC Interrupt Mask Register (SSCIM) Access Offset Address Reset Value : read/write : A4H : 00000000H 16 0000H 15 SSCIM IMTX
0 0 0 0 0 0 0 0 0 0 0 0 0
31 SSCIM
0
IMTX IMER IMRX
Interrupt Mask Tx `0': Disable SSC transmit interrupt `1': Enable SSC transmit interrupt
IMER
Interrupt Mask Error `0': Disable SSC error interrupt `1': Enable SSC error interrupt
IMRX
Interrupt Mask Rx `0': Disable SSC receive interrupt `1': Enable SSC receive interrupt
Note 1: The transmit interrupt notifies the CPU about the start of a transmission. Note 2: The receive interrupt transports the receive data to the shared memory. Note 3: The error interrupt notifies the CPU about different error conditions of data transmission and reception. To further specify what sort of error interrupt the user wants to trace, the corresponding bit of the SSC control register SSCCON has to be set. The SSC error conditions that can be checked are transmit errors (SSCCON(8) = `1'), phase errors (SSCCON(10) = `1') and baud rate errors (SSCCON(11) = `1'). If any of these error conditions shall not be checked, the corresponding bit has to be set to `0'. Example To check for transmit errors only: SSCIM(1) = `1', SSCCON(8) = `1', SSCCON(10) = `0',SSCCON(11) = `0' Note: SSCCON(9) always has to be set to zero!
Data Sheet
257
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Slave Register Descriptions
11.2.6
IOM(R)-2 Registers
This section contains descriptions of all IOM(R)-2 slave registers. IOM(R)-2 Control Register 1 (IOMCON1) Access Offset Address Reset Value : write/read : B0H : 000000FFH 16
0 0 0 SWR EXL ENIH CLR 0 0 0 EOM MXR MRR 0 0
31 IOMCON1 0 15 IOMCON1 AS SWR
MSN(2:0) MRIM MRC MXIM MXC
7
IMCH (7:0)
0
Software Reset `1': Resets and keeps the IOM(R)-2 handler in its initial state. `0': Normal operation.
EXL
External Loop `0': Disables the external loop. `1': Enables an external test loop: Incoming data (MON, C/I, MR and MX) are mirrored to the M32X output line.
ENIH
Enable IOM(R)-2 Handler `1': Enables IOM(R)-2 handler. Note: Set to `1' as part of the initialisation whenever IOM(R)-2 operation is used.
CLR
Clock rate The IOM(R)-2 clock rate is related to the IOM(R)-2 data rate: `0': Single data rate. `1': Double data rate.
Data Sheet
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Slave Register Descriptions EOM End of Monitor Data Stream `0': No further Data will be loaded into the Monitor Transmit FIFO. The IOM(R)-2 handler generates MX = `1' during 2 consecutive IOM(R) frames, after last data has been sent out of the transmit FIFO. `1': Data loaded in the Monitor Transmit FIFO (2 bytes deep) belong to one large data packet (e.g. 8 bytes) and are sent directly after FIFO write access. No EOM condition is generated. MXR Monitor Transmit FIFO Reset `1': Resets the transmit FIFO and keeps the transmit part in its initial state. `0': Normal operation. MRR Monitor Receive Reset `1': Resets and keeps the receiver in its initial state. `0': Normal operation. Note: MRR = `1' also affects the transmit part; set to `0' for normal operation even if monitor receive is not used. AS Auto Search `0': The monitor handler is allocated to one monitor channel which number is programmed in the MSN field. `1': The monitor handler searches for an active monitor channel on the IOM(R) interface (receive data line). It generates an interrupt upon reception of a MX = `0'. The interrupt vector contains the IOM(R) monitor subframe number of the selected monitor channel. Note: Prior to starting the read procedure, this IOM(R) monitor subframe number must be loaded into the MSN bit field first. MSN (2:0) MRIM Monitor Subframe Number Address of the active monitor channel (one out of 8). Monitor Channel Receiver Interrupt Mask `0': Monitor receiver interrupts are not masked (are enabled) `1': Monitor receiver interrupts are masked. MRC Monitor Channel Receiver Control `0': Monitor receiver is disabled (OFF) `1': Monitor receiver is enabled (ON)
Data Sheet
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Slave Register Descriptions MXIM Monitor Channel Transmitter Interrupt Mask `0': Monitor transmitter interrupts are not masked (are enabled) `1': Monitor transmitter interrupts are masked. MXC Monitor Channel Transmitter Control `0': Monitor transmitter is disabled (OFF) `1': Monitor transmitter is enabled (ON) IMCH (7:0) Interrupt Mask Channel-wise Interrupt on the IOM(R) subchannel corresponding to the bit field number is: `0': enabled `1': masked (Monitor and C/I interrupts).
Data Sheet
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Slave Register Descriptions IOM(R)-2 Control Register 2 (IOMCON2) Access Offset Address Reset Value : write/read (bits 3 to 6 read only) : B4H : 00000000H 16
0000H
31 IOMCON2 15 IOMCON2 TMO
00H
7
0 TMO CIT1 CIT0 CON1 ASIM
0
MOIM CIIM
IOMTMO Access Indicator A write access to the IOMTMO register is `0': allowed `1': not allowed. This bit is readable only.
CIT1
IOMCIT1 Access Indicator A write access to the IOMCIT1 register is `0': allowed `1': not allowed. This bit is readable only.
CIT0
IOMCIT0 Access Indicator A write access to the IOMCIT0 register is `0': allowed `1': not allowed. This bit is readable only.
CON1
IOMCON1 Access Indicator A write access to the IOMCON1 register is `0': allowed `1': not allowed. This bit is readable only.
Data Sheet
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Slave Register Descriptions ASIM Auto Search Interrupt Mask The monitor handler generates an interrupt upon Auto Search. This interrupt is: `0': enabled `1': masked. MOIM Monitor Interrupt Mask The monitor handler generates interrupts upon receiving or transmitting monitor data. The interrupts MEM, MRFF, MTFF and MAB are: `0': enabled (refer to the IOMSTAT register and Section 8.3.1) `1': masked CIIM C/I Interrupt Mask The C/I handler generates an interrupt upon a detection of a change in one of 8 C/I fields (double last look). This interrupt is: `0': enabled (refer to Section 8.3.2) `1': masked
Data Sheet
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Slave Register Descriptions IOM(R)-2 Status Register (IOMSTAT) Access Offset Address Reset Value : read : B8H : 01008000H 16
0 0 0 0 0 X RIP 0 0 0 AMCF CSA CNO(2:0)
31 IOMSTAT 0 15 IOMSTAT MFR MFA MTO X RIP
MEM MRFF MTFE MAB
7
XXH
0
Reset in Progress `1': A software reset or a monitor FIFO reset (SWR, MXR or MRR) are currently in progress
AMCF
Active Monitor Channel Found `1': Indicates, that autosearch function has found a channel with an active monitor transmit bit. The channel number is coded in CNO(2:0).
CSA CNO
Channel Search Active `1': The autosearch function is active. Channel Number Contains the coding for the IOM(R)-2 channel 0 ... 7, in which the autosearch function has found an active monitor transmit bit.
MFR
Monitor Transmit FIFO Ready `0': The transmit FIFO is full `1': The transmit FIFO is not full; 1 or 2 bytes may be storred in the transmit FIFO
MFA
Monitor Receive FIFO Data Available `0': The receive FIFO is empty `1': The receive FIFO is not empty; 1 or 2 bytes may be read out of the FIFO
Data Sheet
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Slave Register Descriptions MTO Monitor Timeout `1': A monitor timeout has occured. This bit is set when the transmitter does not receive an active MR-bit after data transmission is started. For further data transmission the IOM controller needs to be resetted via the bit RST2 in the PCI configuration register PCIRES (see "PCI Configuration Space Reset Register" on Page 141). MEM MRFF MTFE MAB X or XXH Monitor End of Message `1': A complete monitor data message has been received. Monitor Receive FIFO Full `1': The receive FIFO is full Monitor Transmit FIFO Empty `1': The transmit FIFO is empty Monitor Abort `1': A monitor abort was detected. Do not care
Data Sheet
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Slave Register Descriptions IOM(R)-2 C/I Code Tx Register Channels 0 ... 3 (IOMCIT0) Access Offset Address Reset Value : write/read : C0H : FEFEFEFEH 16 1 COM3 1 0 1 1 COM2 1 0 0 1 COM1 1 0 1 1 COM0 1 0
31 IOMCIT0 1 15 IOMCIT0 COMn 1
Command in C/I Channel 3 ... 0) Contains the IOM(R)-2 C/I information (4 bits) for channel 3 ... 0 in transmit direction.
IOM(R)-2 C/I Code Tx Register Channels 4 ... 7 (IOMCIT1) Access Offset Address Reset Value : write/read : C4H : FEFEFEFEH 16 1 COM7 1 0 1 1 COM6 1 0 0 1 COM5 1 0 1 1 COM4 1 0
31 IOMCIT1 1 15 IOMCIT1 COMn 1
Command in C/I Channel 7 ... 4 Tx Contains the IOM(R)-2 C/I information (4 bits) for channel 7 ... 4 in transmit direction.
Data Sheet
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Slave Register Descriptions IOM(R)-2 C/I Code Rx Register Channels 0 ... 3 (IOMCIR0) Access Offset Address Reset Value : read : C8H : 00000000H 16 0 IND3 X 0 0 0 IND2 X 0 0 0 IND1 X 0 0 0 IND0 X 0
31 IOMCIR0 0 15 IOMCIR0 INDn 0
Indication in C/I Channel 3 ... 0 Contains the IOM(R)-2 C/I information (4 bits) for channel 3 ... 0 in receive direction.
X
Do not care
IOM(R)-2 C/I Code Rx Register Channels 4 ... 7 (IOMCIR1) Access Offset Address Reset Value : read : CCH : 00000000H 16 0 IND7 X 0 0 0 IND6 X 0 0 0 IND5 X 0 0 0 IND4 X 0
31 IOMCIR1 0 15 IOMCIR1 INDn 0
Indication in C/I Channel 7 ... 4 Contains the IOM(R)-2 C/I information (4 bits) for channel 7 ... 4 in receive direction.
X
Do not care
Data Sheet
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Slave Register Descriptions IOM(R)-2 Tx Monitor Register (IOMTMO) Access Offset Address Reset Value 31 IOMTMO 15 IOMTMO TMB1 TMB0 TMB1 Transmit Monitor Byte 1 Contains the byte 1 of the IOM(R)-2 transmit monitor channel information. Transmit Monitor Byte 0 Contains the byte 0 of the IOM(R)-2 transmit monitor channel information. Note: Immediately after write access to TxMonitor Register IOMTMO the two bytes TMB0 and TMB1 are sent. The value of bit field MSN(2:0) in register IOMCON1 determins the monitor subframe number which is used. IOM(R)-2 Rx Monitor Register (IOMRMO) Access Offset Address Reset Value 31 IOMRMO 15 IOMRMO RMB1 RMB0 FFH FFH 0 : read : D4H : FFFFFFFFH 16 TMB0 FFH FFH 0 : write/read : D0H : FFFFFFFFH 16
Data Sheet
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Slave Register Descriptions RMB1 RMB0 Receive Monitor Byte 1 Contains the byte 1 of the IOM(R)-2 receive monitor channel information. Receive Monitor Byte 0 Contains the byte 0 of the IOM(R)-2 receive monitor channel information.
Data Sheet
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Slave Register Descriptions
11.2.7
Mailbox Registers
This section contains descriptions of all Mailbox slave and LBI accessible registers. Mailbox Command Register (MBCMD) Access Offset Address (slave register from PCI host system) Address coding (pins LA(2:0) from LBI peripheral) Reset Value 31 MBCMD 15 MBCMD MBINT(15:1) 0000H 0 INPCI/ INLBI : read/write : E0H : 000B : 00000000H 16
INPCI
Mailbox Interrupt from PCI Host System This bit regulates the exclusive access of the Mailbox Data Registers from PCI host system. Read access: Returns the value written to the INLBI bit field from the LBI peripheral. Write access: `1': Generates interrupt on LBI side by assertion of LINTO signal (a mailbox interrupt vector with the contents of bits MBINT(15:1) is generated). The interrupt signal may be deasserted by writing a `1' to the MBI bit field in Status Acknowledge Register STACK.
Data Sheet
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Slave Register Descriptions INLBI Mailbox Interrupt from Intelligent LBI Peripheral This bit regulates the exclusive access of the Mailbox Data Registers from LBI peripheral. Read access: Returns the value written to the INPCI bit field from host PCI system. Write access: `1': Generates an interrupt on PCI side by assertion of INTA signal (a mailbox interrupt vector with the contents of bits MBINFO(15:1) is generated). The interrupt signal may be deasserted by reading MBCMD. MBINT Mailbox Interrupt Information from PCI/LBI User programmable bit fields to pass interrupt information from PCI host system on to LBI peripheral and vice versa. A read access from one side of the Mailbox returns the MBINT values that the other side had written to.
Data Sheet
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Slave Register Descriptions Mailbox Data Register 1 ... 7 (MBDATA1 ... MBDATA7) Accesses Offset Addresses (slave registers from PCI host system) Address codings (pins LA(2:0) from LBI peripheral) Reset Values 31 MBDATA1 15 MBDATA1 MBDATA1(15:0) 0000H 0 : read/write : E4H, E8H, ECH, F0H, F4H, F8H, FCH : 001B, 010B, 011B, 100B, 101B, 110B, 111B : 00000000H 16
Used for data transfer between PCI interface and LBI and vice versa. For 16-bit LBI accesses, bits 15 ... 0 are used to transfer data; whereas in case of 8-bit LBI accesses, only bits 7 ... 0 are used. Note: The seven Mailbox Data Registers have the same structure (refer to Section 6.1.4).
Data Sheet
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Slave Register Descriptions
Data Sheet
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Host Memory Organization
12
12.1
Host Memory Organization
Control and Configuration Block (CCB) in Host Memory
The architecture of the MUNICH32X uses two different Control and Configuration Blocks in host memory, as illustrated in Figure 79 and Figure 80: 1. related to the serial PCM core (CCB) 2. related to the LBI (LCCB). Note that each address in CCB/LCCB is DWORD aligned (i.e., the two least significant address bit fields must be set to `0').
12.1.1
Serial PCM Core CCB
The Figure 29 shows the size of the CCB sections: Table 29 Section Action Specification Command Reserved Time Slot Assignment Channel Specification Current Rx Descriptor Addresses Current Tx Descriptor Addresses Sizes of the Control and Configuration Block Number of DWORDs 1 2 32 128 32 32
The reserved section, located after the Action Specification, maintains backward compatibility with the MUNICH32, PEB 20320.
Data Sheet
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Host Memory Organization
CCBA Control Start Address
Receive DATA Channel 0
Action Specification Reserved Time Slot 0 Assignment
Receive Descriptor Channel 0 Time Slot 31 Assignment Transmit DATA Channel 0 Receive Descriptor Channel 0 Channel 0 Specification Last 8 Blocks not used in T1/DS1 Mode
Transmit Descriptor Channel 0
Transmit Descriptor Channel 0
Channel 31 Specification Current Receive Descriptor Address Channel 0
Current Receive Descriptor Address Channel 31 Current Transmit Descriptor Address Channel 0
Current Transmit Descriptor Address Channel 31 Control and Configuration Section
ITD10375
Figure 79
Serial PCM Core Control and Configuration Block (CCB)
Data Sheet
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Host Memory Organization
12.1.2
LBI CCB
The following table shows the size of the LCCB sections: Table 30 Section Action Specification Command Channel Specification Current Rx Descriptor Addresses Current Tx Descriptor Addresses Sizes of the LBI Control and Configuration Block Number of DWORDs 1 4 2 2
LCCBA Register Receive DATA Channel 0 Control Start Address
Action Specification Receive Descriptor Channel 0 Channel 0 Specification Channel 1 Specification Current Receive Descriptor Address Channel 0 Transmit Descriptor Channel 0 Current Receive Descriptor Address Channel 1 Current Transmit Descriptor Address Channel 0 Current Transmit Descriptor Address Channel 1 LBI Control and Configuration Block (LCCB) Transmit Descriptor Channel 0
ITD10376
Receive Descriptor Channel 0
Transmit DATA Channel 0
Figure 80
LBI Control and Configuration Block (LCCB)
Data Sheet
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Host Memory Organization
12.2
Action Specification
The action specification is read once after each action request (initiated via bit field ARPCM for serial PCM core related action request or ARLBI for LBI related action request in Command Register CMD). All actions are selected by setting the corresponding action specification bit field to `1'.
12.2.1
31
Serial PCM Core Action Specification
16 0000H
15
IN ICO 0 Channel Number 0 RES LOC LOOP LOOPI IA 0
0
0
IN:
Initialization procedure; setting this bit to one causes MUNICH32X to fetch all the time slot assignments and the channel specification of the selected channel (channel number). To avoid collision all time slots being reinitialized should be in a deactivated mode, i.e. the receive and transmit channels must be switched off. Initialize Channel Only; only the channel specification of the selected channel (channel number) is read and reconfigured. RESET; a single initialization procedure is performed. The time slot assignment and all channel specifications are written into the CSR. All time slots are reinitialized.
ICO: RES:
Note: The bits IN, ICO, RES are mutually exclusive within one action specification. They establish different ways of initializing, configuring and reconfiguring the channels and time slots of the MUNICH32X. IA: Interrupt Attention; a new interrupt queue has been defined. The interrupt counter is reset.
Data Sheet
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Host Memory Organization For test purposes, four different loops can be switched at the serial interface using the following coding of the bit fields LOC, LOOP, LOOPI: LOC 0 0 0 0 1 1 1 1 LOOP 0 0 1 1 0 0 1 1 LOOPI 0 1 0 1 0 1 0 1 Interpretation no loop complete internal loop complete external loop switch loops off not allowed channelwise internal loop channelwise external loop not allowed
The loops have the following functions: - Complete external loop The serial data input is physically mirrored back to the serial data output. The time and strobe signals for receive and transmit direction must be identical. - Complete internal loop The serial data output is physically mirrored back to the serial data input. The data on the external input line are ignored. The logical channels have to be programmed identically. The time and strobe signals for receive and transmit direction must be identical. - Channelwise external loop One single logical channel is mirrored logically from serial data input to serial data output. The other channels are not affected by this operation. The data rate for this single logical channel must be identical for receive and transmit direction. - Channelwise internal loop One single logical channel is mirrored logically from serial data output to serial data input. The other channels are not affected by this operation. The data rate for this single logical channel must be identical for receive and transmit direction. All loops of the MUNICH32X are under complete software control. Loops can be closed and opened via software. Note that a more detailed description of the test loops will be provided later in the Application Notes section. Handling of the Loops 1. Switch on loops: RES = IN = ICO = `0' LOC, LOOP, LOOPI PCM, MFL CHANNEL NUMBER determine the selected loop type do not change the previous values in case of channelwise loops use the selected channel number; in case of complete loops use channel number of an active channel.
Data Sheet
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Host Memory Organization 2. Switch off loops: RES = IN = ICO = `0' LOC = `0', LOOP = LOOPI = `1' afterwards: RES = IN = ICO = `0' LOC = LOOP = LOOPI = `0' PCM, MFL CHANNEL NUMBER
do not change the previous values use channel number used with the `switch on loop'
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initialization Procedure Read the complete time-slot assignment and the channel spec. of the specified channel (channel number). Initialize Channel Only Only the channel spec. of the selected channel (channel number) is read and reconfigured.
IN ICO
0
0
Channel Number Channel No. Used in conjunction with IN and ICO
0
RES LOC LOOP LOOPI IA
Loops 000 001 010 011 100 101 110 111 Reset
00
Interrupt Attention A new interrupt queue has been defined. The interrupt address offset is reset.
No Loop Complete Internal Loop Complete Internal Loop Switch Loops off Not Allowed Channel wise int. Loop Channel wise ext. Loop Not Allowed
Read the complete time-slot assignment Read all channel specifications Reinitialize all time-slots
ITD10377
Figure 81
Serial PCM Core Action Specification
Data Sheet
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Host Memory Organization
12.2.2
LBI Action Specification
The LBI action specification is different from the serial PCM core action specification; it provides only the bit fields ICO, IA (same functionality) and a single bit field CHN to address the LBI channel A (`0') or B (`1'), replacing the 5 channel number bit fields of the PCM action specification. 31 0000H 15
0 ICO 0 0 0 0 0 CHN 0 0 0 0 0 IA 0
16
0
0
Data Sheet
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Host Memory Organization
12.3
Serial PCM Core Interrupt Vector Structure
When an serial PCM core interrupt occurs, the MUNICH32X writes the interrupt information and the channel number into the interrupt circular buffer (either receive or transmit direction). At the same time it generates an interrupt pulse. The classes of error (e.g., host initiated interrupt or CRC error) of a channel in one direction are treated independently of each other. If several interrupt events coincide they will be indicated to the host with one shared interrupt. Note that two seperate interrupt vectors for receive and transmit direction exist. In receive direction, the interrupt vector is located at the shared memory address of RIQBA register. In receive direction, the interrupt vector is located at the address of TIQBA register. Serial PCM Core Interrupt Vector Rx Direction 31 RX_IV 0 16 RX_IV
SB SA X HI FI IFC SF ERR FO 0 0 Channel Number
16 0 1 1 0 0 0 0 FRC E7 E6 E5 E4 E3 E2 E1 0
Data Sheet
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Host Memory Organization Serial PCM Core Interrupt Vector Tx Direction 31 TX_IV 0 16 TX_IV
0 0 0 HI FI 0 0 ERR FO FE2 Late Stop Channel Number
16 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note that the bit order has changed from the MUNICH32 (PEB 20320). The significant changes of the contents are the additional FE2 and Late Stop bits.
Data Sheet
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Host Memory Organization Bit Assignment For Interrupt Queue Registers Channel specific interrupts indicate specific events in the channel encoded by `Channel Number' in Rx or Tx Interrupt Queue Register. The interpretation of these interrupts depends on the specification of the channel in which they occur. The following table shows which interrupts can occur in which mode (unused bits are always `0'). 31
0 0 1 R/T RT RT RT RT 0 0 0 0 FRC E7 E6 E5 E4 E3 E2
16
E1
HDLC
0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
V.110/X.30 0 TMA TMB/TMR 0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
15
SB SA X HI FI IFC SF ERR FO FE2 Late Stop R R RT RT RT RT RT RT RT RT T TI Channel Number
0
HDLC
0
0
R
0
R
RT RT RT RT
X X X X
X X X X
X X X X
X X X X
X X X X
V.110/X.30 R TMA TMB/TMR Where `0' `R' 0 0
0 T
0 0 0
0 0 0
0 T T
0 0 0
0 0
0 0
RT RT
means that the bit is always `0' for this mode means a bit that can only be set in the receive direction, i.e. may only be `1' if RT is `1' `T' means a bit that can only occur in transmit direction, i.e. may only be `1' if RT is `0' `RT' means a bit that can occur in receive or transmit direction `X' means a bit fixed by the channel and direction (Rx, Tx) of the event it belongs to. `TI' means transmit in conjunction with DRDY pin (in IOM(R)-2 mode and HDLC)
Data Sheet
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Host Memory Organization
12.4
Interrupt Bit Field Definitions
The functions of the interrupt bits depend on the protocol mode. They are therefore discussed bit by bit, indicating the different meanings in each mode. R/T: FRC: (all modes) Determines the direction of the interrupt (`1' = Rx, `0' = Tx). (V.110/X.30 mode, receive direction only) Change of the framing (E, S, X) bits of the V.110/X.30 frame detected. This interrupt is generated whenever a change in the E-, S-, X-bits is detected, but at most one time within one frame of 10 octets, even if there is more than one change within the frame. After detecting a receive abort channel command for one 10-octet frame FRC is also issued. (V.110/X.30 mode, receive direction only, only in conjunction with FRC) The value of the bits Ex, Sx, X in the received V.110/X.30 frame. If a value changes e.g., two times within the same frame, only the final change is reported. If the change was caused by a receive abort channel command all bits are 0. (all modes, all directions) Host initiated Interrupt; this bit is set when the MUNICH32X detects the HI bit in the Rx or Tx descriptor and branches to the next descriptor, or starts polling the HOLD bit if set. 1.1 HDLC, TMB, TMR Receive Direction: FI = 1 indicates, that a frame has been received completely or was stopped by a receive abort channel command or fast receive abort or a HOLD in a Rx descriptor. It is set when the MUNICH32X branches from the last descriptor belonging to the frame to the first descriptor of a new frame. It is also set when the descriptor in which the frame finished contained a HOLD bit, the interrupt is then issued when the MUNICH32X starts polling the HOLD bit. 1.2 HDLC, TMB, TMR, TMA Transmit Direction: issued if the FE bit is detected in the Tx descriptor. It is set when the MUNICH32X branches to the next Tx descriptor, belonging to a new frame, or when it starts polling the HOLD bit if set in conjunction with the FE bit; ERR and FI are set if a Tx descriptor contains a HOLD bit, but no FE bit IFC: (HDLC mode, Receive direction only) Idle/Flag Change; an interrupt is generated in HDLC if the device changes the interframe time-fill (ITF) state. After reset, the device is in the ITF idle state. It changes to the ITF flag state if it receives two consecutive flags with or without shared zeros. It changes back to the ITF
283 2001-02-14
Ex, Sx, X:
HI:
FI:
Data Sheet
PEB 20321 PEF 20321
Host Memory Organization idle state upon reception of 15 contiguous `1'-bits or when a receive abort channel command is active during 15 received bits. SF: (HDLC mode, Receive direction only, always in conjunction with FI) Short frame detected A frame with 16 bits between start flag and end flag or end abort flag for CRC16 32 bits between start flag and end flag or end abort flag for CRC32 has been detected. The sequences 7E 7FH and 7E FEH and 7E FFH are also short frames. SF is always in conjunction with ERR except for the frames 7E00 007EH for CRC16 7E00 0000 007EH for CRC32 always in conjunction with FI = 1 1.1 HDLC mode Receive Direction One of the following receive errors occurred - FCS of the frame was incorrect - the bit length of the frame was not divisible by 8 - the byte length exceeded MFL - the frame was stopped by 7FH - the frame could only be partly stored due to internal buffer overflow of RB - the frame was ended by a receive abort channel command - the frame could not be transferred to the shared memory completely because of a HOLD bit set in a Rx descriptor not providing enough bytes for the frame. - the frame was aborted by a fast receive abort channel command A more detailed error analysis can be performed by the status information in the Rx descriptor. 1.2 HDLC mode Transmit Direction one of the following transmit errors occurred: - the last descriptor had HOLD = 1 and FE = 0 - the last descriptor had NO = 0 and FE = 0 2.1 V.110/X.30 mode Receive Direction one of the following receive errors occurred: - data could only partly be stored due to internal buffer overflow of RB - 3 consecutive frames had an error in the synchronization pattern (loss of synchronism) - a fast receive abort channel command was issued - the data could not be transferred to the shared memory completely because of a HOLD bit set in a Rx descriptor not providing enough bytes for the data
Data Sheet 284 2001-02-14
ERR:
PEB 20321 PEF 20321
Host Memory Organization - a receive abort channel command was active for at least 3 consecutive frames A more detailed error analysis can be performed by the status information in the Rx descriptor. 2.2 V.110/X.30 mode Transmit Direction one of the following transmit errors occurred - the last descriptor had a HOLD = 1 or FE = 1 - the last descriptor had FE = 0 and NO = 0 3.1 TMA mode Receive Direction one of the following errors occurred - the data could not be transferred to the shared memory completely because of a HOLD bit set in a Rx descriptor not providing enough bytes for the data - a fast receive abort channel command was issued 3.2 TMA mode see Chapter 1.2 Transmit Direction
4.1 TMB/TMR mode Receive Direction always in conjunction with FI = 1 one of the following receive errors occurred - the bit length of the frame was not divisible by 8 - the frame could only be partly stored due to internal buffer overflow of RB - the frame could not be transferred to the shared memory completely because of a HOLD bit set in a Rx descriptor not providing enough bytes for the frame - the frame was aborted by a fast receive abort channel command A more detailed error analysis can be performed by the status information in the Rx descriptor. 4.2 TMB/TMR mode see Chapter 1.2 FO: Transmit Direction
1.1 HDLC, TMB, TMR Receive Direction The MUNICH32X has discarded one or more whole frames or short frames or change of interframe time-fill informations due to inaccessibility of the internal buffer RB. 1.2 HDLC, TMB, TMR Transmit Direction The MUNICH32X is unable to access the shared memory in time or has detected a fatal bus cycle error during a read access on the transmit data section. The current erroneous frame is aborted with a `0' and 14 `1' for HDLC, with `00' for TMB and `0000' for TMR; afterwards interframe timefill is sent until the MUNICH32X can access again the shared memory.
Data Sheet
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Host Memory Organization The MUNICH32X will read the transmit data from the location which should be accessed before the Tx-FO happened and transmit the rest of the erroneous frame. 2.1 V.110/X.30 Receive Direction The MUNICH32X has discarded a loss of synchronism information or a change of a E-, S-, X-bits information due to inaccessibility of the internal buffer RB. 2.2 V.110/X.30 Transmit Direction The MUNICH32X is unable to access the shared memory in time. It generates three 10-octet frames with framing errors and restarts with the next error-free Tx data. 3.1 TMA Receive Direction The MUNICH32X has discarded data due to inaccessibility of the internal buffer RB. 3.2 see Chapter 1.2 FE2: HDLC, TMA, TMB/TMR Transmit Direction Indicates that data has been sent (including CRC) Note that this provides a Tx End-of-Packet interrupt capability which allows host software to free-up Tx buffers after the contents have been completely transferred to the MUNICH32X. Late Stop: HDLC Transmit Direction (IOM(R)-2 mode only) Indicates that the DRDY pin has been asserted while transmission of data took place on an IOM(R)-2 D-channel (refer to IOM(R)-2 interface description in Chapter 8). If DRDY is asserted after the MUNICH32X prepared at least the first data bit of a packet for sending or was already sending a packet, these prepared or sent data are lost; the current descriptor has to be retransmitted. In order to clean up the transmit buffer a `Transmit Off' command followed by a `Transmit Init' command together with NITBS = `1' must be issued for the corresponding channel (refer to Channel Specification description in Chapter 12.6).
Data Sheet
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Host Memory Organization The following table shows which interrupt bits fields may be masked by channel specification bits. 31
0 0 0 R/T 0 0 0 0 FRC E7 E6 E5 E4 E3 E2
16
E1
Receive Transmit
- -
- -
- -
- -
- -
- -
- -
- -
CH CH CH CH CH CH CH CH
-
-
-
-
-
-
-
-
15
SB SA X HI FI IFC SF ERR FO FE2 Late Stop RE Channel Number
0
Receive Transmit
CH CH CH
-
FIR IFC SFE RE
-
- -
- -
- -
- -
- -
- -
-
-
-
- FIT
-
-
TE
TE FE2
Data Sheet
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2001-02-14
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Host Memory Organization
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
FRC E7 E6 E5 E4 E3 E2 E1 SB SA X HI FI IFC SF ERR FO FE2 Late Stop R/T
4
3
2
1
0
001
0000
Channel Number Channel Number
Framing Bits Changed V.110/X.30 mode received E, S, X Bits changed Direction 0 Transmit Interrupt 1 Receive Interrupt
Identifies the channel where the interrupt occurred. Late Stop
Frame End Indicates that data has been sent Overflow/Underflow Internal buffer not available Protocol Error e.g. CRC error, frame aborted, loss of synchronization (V.110/X.30) : MFL exceeded Internal buffer overflow/underflow Short Frame Host Initiated Interrupt HI Bit in the Rx/Tx descriptor was set HDLC mode, in conjunction with FI (empty HDLC frame or incorrect HDLC frame, nothing stored in memory)
Frame Indication Interframe Timefill Change End of receive or transmit frame indication HDLC receiver detected change in ITF state
ITD10378
Figure 82
Interrupt Information
Data Sheet
288
2001-02-14
PEB 20321 PEF 20321
Host Memory Organization
12.5
Time Slot Assignment
The time slot assignment is read once after each action request (initiated via bit ARPCM in Command Register CMD) having the action specification bit IN or RES set. Note: The Time Slot Assignment is not applicable for the LBI block. It provides the cross reference between the 32 (24) time slots of the PCM highway and the data channels (up to a maximum number of 32). The data channels can be composed of different Rx and Tx time slots, which have individual bit rates. With the concept of subchanneling, MUNICH32X can perform flexible transmission from 8 Kbit/s up to 2.048 Mbit/s per channel. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 TTI Tx Channel Number TTI Tx Channel Number Tx Fill Mask Tx Fill Mask time slot 0 time slot 1 ...
0
0
TTI TX Channel Number 9 8 7 6 5
Tx Fill Mask 4 3 2 1 0
time slot 31
15 14 13 12 11 10 0 0
0 RTI Rx Channel Number 0 RTI RX Channel Number
Rx Fill Mask RX Fill Mask
time slot 0 time slot 1 ...
0
0 RTI Rx Channel Number
Rx Fill Mask
time slot 31
Fill/Mask Code:
For bit rate adaption the fill/mask code determines the number of bits and the position of these bits within the time slot. For all modes the bits selected by Fill/Mask = `1' in the slots of a channel are concatenated, those with Fill/Mask = `0' are ignored/tristated in Rx/ Tx direction.
Channel Number: The channel number identifies the data channel. Its transmission mode is described in the respective channel specification. TTI: Tx Time slot Inhibit; setting this bit to `1' causes MUNICH32X to tristate the Tx time slot. The data is not destroyed but sent in the next not tristated time slot allocated to this channel.
Data Sheet
289
2001-02-14
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Host Memory Organization RTI: RX time Slot Inhibit; setting this bit to `1' causes MUNICH32X to ignore the received data in the time slot. The channel is not processed in this time slot.
Note: It is recommended to set the inhibit bits `TTI' and `RTI' on any unused time slot.
Data Sheet
290
2001-02-14
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Host Memory Organization
12.6
Channel Specification
The channel specification is read once after each action request (initiated via bits ARPCM/ARLBI in Command Register CMD) having the action specification bit IN, RES or ICO set. Note that RES applies to the channel specifications of all channels, IN and ICO only apply to the channel specification of the channel indicated in the action specification. PCM Core: 31 30 29 28 27 26 25 24 23 NITBS FRDA FTDA 0 0 0 0 0 0 9 0 8 0 0 7 FRDA FTDA 0 LBI: 31 30 29 28 27 26 25 24 23 NITBS FRDA FTDA 0 0 0 0 0 0 9 0 8 0 0 7 FRDA FTDA 0 0 0 0 0 0 0 0 0 0 ITBS 0 6 0 5 0 4 0 3 FA 0 2 1 0 1 1 0 0 IFTF 22 21 20 19 18 17 16 Interrupt Mask Channel Command 0 0 0 0 0 0 0 0 0 ITBS 0 6 0 5 0 4 0 3 FA 0 2 0 1 0 0 IFTF 22 21 20 19 18 17 16 Interrupt Mask Channel Command
15 14 13 12 11 10 TFLAG
TFLAG/CS INV CRC
TRV
Mode
15 14 13 12 11 10 TFLAG
TFLAG/CS INV CRC
TRV
Data Sheet
291
2001-02-14
PEB 20321 PEF 20321
Host Memory Organization Interrupt Mask: PCM Core: 31 FE2 LBI: 31 FE2 30 0 29 0 28 0 27 TE 26 RE 25 FIR 24 FIT 30 SFE 29 IFC 28 CH 27 TE 26 RE 25 FIR 24 FIT
These bits mask the bits in the interrupt information DWORD according to the table at the end of Section 12.4 (interrupt bit fields definition). If an event leads to an interrupt with several bits set (e.g. FI and ERR) masking only a proper subset of them (e.g. ERR) will lead to an interrupt with the nonmasked bits set (e.g., FI). If all bits of an event are masked, the interrupt is suppressed. The interrupt mask is therefore bit specific and not event specific. NITBS: New ITBS value; if this bit is set the individual Tx buffer size ITBS is valid and a new buffer field of TB is assigned to the channel. In this process first the occupied buffer locations of the channel are released and then according to ITBS a new buffer area is allocated. If there is not enough buffer size in TB (occupied by other channels) the process will be aborted and an action request failure interrupt is generated. After aborting no buffer size is allocated to the channel. For preventing action request failure enough buffer locations must be available. This can be done by reducing the buffer size of the other channels. To avoid transmission errors all channels to be newly configured must be deactivated before processing.0 Note: ITBS has to be set to `0' if NITBS = `0'. NITBS should be set to `0' in conjunction with a transmit abort channel command. Note: For LBI channels ITBS has to be set to `10H', if NITBS is set to `1'.
Data Sheet
292
2001-02-14
PEB 20321 PEF 20321
Host Memory Organization Channel Command: PCM Core: 22 RI LBI: 22 RI 21 TI 20 0 19 0 18 TH 17 0 16 RA 21 TI 20 TO 19 TA 18 TH 17 RO 16 RA
These bits allow the channel to be initialized, aborted or reconfigured at the serial PCM side as well as at the P side. These bits can be decomposed in 3 independent command groups: RI, RO, RA form the receive command group TO, TI, TA the first transmit command group and TH is the second transmit command group. In the following section, the functionality of these bits is discussed according to the groups. 1. Receive Command Group - Receive Clear (not supported by LBI) RI = 0, RO = 0, RA = 0 (clears a previous receive abort or receive off condition, affects only the serial interface) The effect of this command depends on the previous history of the channel * if the channel was never initialized by a receive initialization command it has no effect * if it was initialized previously it clears a receive off or receive abort condition set by a previous channel command * if no receive off or receive abort condition is set it has no effect. - Fast Receive Abort (not supported by LBI) RI = 0, RO = 0, RA = 1 (clears a previous receive abort or receive off condition, affects only the DMA interface) This abort is performed in the DMA controller and does not interfere with the reception on the serial interface and the transfer of the data into the Rx buffer. If this abort is detected the current Rx descriptor is suspended with an abort status (RA bit set to `1') followed by a branching to the new descriptor (FRDA) defined in the channel specification of the CCB. For HDLC, TMB, TMR the rest of a frame which was only partially transferred before suspension of the Rx descriptor is aborted, the new descriptor is related to the next
Data Sheet 293 2001-02-14
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Host Memory Organization frame. An interrupt with FI, ERR is issued. For V.110/X.30 and TMA data bits might get lost. An interrupt with ERR is issued. - Receive Off (not supported by LBI) RI = `0', RO = `1', R = `0' (clears a previous receive abort condition, sets off condition, affects only the serial interface) This channel command sets the receiver into the receive off condition. The receive channel is disabled completely at the serial interface, i.e. the receive deformatter RD is reset and the receive buffer RB is not accessed for this channel. A currently processed frame (HDLC, TMB, TMR mode) is not properly finished with any status information. The data stored in the RB at that time is still transferred to host memory. After the receive off condition is cleared by another channel command: * in HDLC, TMB, TMR (V.110/X.30, TMA) mode the device waits for a new frame (10octet frame, nothing) to begin and then starts filling RB again. If the receive off command lead to an improper finishing of a frame (data, data), the new frame (data, data) is concatenated with the finished one. To avoid this problem there are two suggestions: a) issue a receive abort channel command and wait for 32 (240, 8) bits for this channel to be processed before issuing the receive off command. b) wait in the receive off condition until the RB is emptied for this channel (i.e. for at most 8 PCM frames if the MUNICH32X has sufficient access to the shared memory) and leave the receive off condition by a receive initialization command. The receive off channel command is ignored in case of any kind of loop. - Receive Abort (not supported by LBI) RI = `0', RO = `1', RA = `1' (clears a previous receive off condition, sets a receive abort condition, affects only the serial interface) This receive channel command sets the receiver into the receive abort condition. In this condition it receives (instead of the normally received bits) logical `1' bits for HDLC logical `0' bits for V.110/X.30, TMB, TMR logical `0' bits for TMA mode irrespective of the INV bit. This leads to * For HDLC: a currently processed frame is aborted after 7 received bits for this channel, leading to a RA set in the status of the frame and an interrupt with set FI and ERR bits only or to an interrupt with set SF, FI and ERR bits. If the receiver was in the flag interframe time-fill state it will lead to an interrupt with set IFC bit after 15 received bits. * For V.110/X.30: if the receiver was in the synchronized frame state it will go to the unsynchronized state after 240 bits and issue a LOSS bit in the status of the current Rx descriptor. It will also issue an interrupt with set ERR bit and (unless all E-, S-, X-bits were `0' previously) issue one or two interrupts with FRC set and having all E-, S-, X-bits at `0' in the last one.
Data Sheet 294 2001-02-14
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Host Memory Organization * For TMB: a currently processed frame is aborted after 15 received bits for this channel, leading to an interrupt with FI set but ERR on 0, the status of this frame is always 00H. * For TMR: a currently processed frame is aborted after 31 received bits for this channel, leading to an interrupt with FI set but ERR on 0, the status of this frame is always 00H. Note 1: It is recommended to clear the receive abort condition via a receive off command for V.110/X.30 mode, the TMB and the TMR mode. Note 2: After issuing a receive abort channel command it is advisable to stay in this condition during at least 16, 240, 16, 32, 8 bits of the channel for HDLC, V.110/ X.30, TMB, TMR, TMA respectively. - Receive Jump RI = `1', RO = `0', RA = `0' (clears a previous receive abort or receive off condition, affects only the DMA interface) During normal operation branching to a new descriptor (FRDA) is possible without interrupting the current descriptor and aborting the received frame (HDLC, TMB, TMR) or received data (V.110/X.30, TMA). The DMA controller will proceed finishing the current receive descriptor as usual either with a frame end condition or with the corresponding data buffer completely filled and afterwards branch to the new descriptor specified by FRDA. Thus a received frame may be splitted on `old' and `new' descriptors. - Receive Initialization RI = `1', RO = `0', RA = `1' (clears a previous receive abort or receive off condition, affects the DMA and serial interface) Before the MUNICH32X has got a receive initialization command it will not receive anything properly in a channel. This command should therefore be the first channel command after a reset for a channel to be used. FRDA is then the address of the starting point of the Rx descriptor chaining list. If the command is issued during normal operation it only affects the DMA interface. The current Rx descriptor is suspended without writing the second DWORD with the status, no interrupt is generated. For HDLC, TMB, TMR the rest of a frame which was only partially transferred before the suspension of the Rx descriptor is aborted, the new descriptor (FRDA) is related to the next frame. For V.110/X.30 and TMA data bits might get lost. * General Notes on Receive Commands: 1. After a pulse at the reset pin a channel having a time slot with RTI = `0' should be issued receive off commands until it is used. 2. When the channel is intended to be used, a receive initialize command should be issued before using any other receive channel command. 3. To shut down a channel in receive direction, it should first be set into the receive abort condition for the time specified there and then set into the receive off condition.
Data Sheet
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Host Memory Organization 4. Before changing the MODE, CRC, CS, TRV, INV, TFLAG bits of a channel or its RTI or time slot assignment or its fill/mask bits it should have been shut down. The bits should be changed while issuing the receive off command. 5. To revive a channel after it has been shut down, the receive initialization command should be used. 6. To switch to a new starting point of a Rx descriptor chain one should preferably use the receive jump command, only exceptionally the fast receive abort command and never the receive initialize command. 7. To issue channel commands not affecting the receive side one should issue - a receive clear command if neither a receive off nor a receive abort condition is set - a receive off command if a receive off condition is set - a receive abort command if a receive abort condition is set. 8. Combinations of the bits RI, RO, RA not in this description are reserved and are not allowed to be used. 2. First Transmit Command Group - Transmit Clear (not supported by LBI) TI = `0', TO = `0', TA = `0' (clears a previous transmit abort or transmit off condition, affects only the serial interface) * if the channel was never initialized by a transmit initialization command it has no effect * if it was initialized previously it clears a transmit off or transmit abort condition set by a previous channel command * if no transmit off or transmit abort condition is set it has no effect - Fast Transmit Abort (not supported by LBI) TI = `0', TO = `0', TA = `1' (clears a previous transmit abort or transmit off condition, affects only the DMA interface) This abort is performed in the DMA controller and does not interfere with the current transmission on the serial interface and the transfer between the TF and TB. If this abort is detected the current descriptor is suspended and the frame or data transferred to the TB is aborted. The next frame beginning in the Tx descriptor (FTDA) defined in the channel specification of the CCB will be started immediately. For HDLC, TMB, TMR the first part of the frame of the suspended descriptor is sent and append by 011 1111 1111 1111 for HDLC for TMB at least 00H at least 00 00H for TMR Afterwards the next frame is started. For V.110/X.30 three 10-octet frames with errors in the synchronization pattern are sent after the data of the suspended descriptor, afterwards the next data are sent in correct frames. For TMA a TFLAG (FA = `1') or FFH (FA = `0') is sent in at least one time slot after the data of the suspended descriptor, afterwards the next data are sent.
Data Sheet 296 2001-02-14
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Host Memory Organization - Transmit Off (not supported by LBI) TI = `0', TO = `1', TA = `0' (clears a previous transmit abort condition, sets a transmit off condition, effects only the serial interface) The Tx channel is disabled immediately, i.e. the Tx formatter is reset and the Tx buffer is not accessed for this channel. The output time slots are tristated. Upon leaving the transmit off mode the transmit link list must be initialized by a transmit reinitialize command. Otherwise the transmission will be started with the remaining data still stored in TB and continue with the old link list. If a loop condition is set the transmit off does not reset the Tx formatter, it only tristates the serial output line. After the transmit off condition is cleared by the transmit initialize command. * In HDLC, TMB, TMR, V.110/X.30 the device starts with the interframe time-fill 7E for HDLC and IFTF = `0' FF for HDLC and IFTF = `1' 00 for TMB, TMR, V.110/X.30 and then with the frame in the descriptor at FTDA. For V.110/X.30 this descriptor must have the V.110-bit set and point to the E-, S-, X-bits, the data are then at the next Tx descriptor. * In TMA mode the device starts with the interframe time-fill TFLAG for FA = `1' for FA = `0' FFH and then with the data in the descriptor at the FTDA. Note: It is recommended to set bit-field `Mode' located in the first DWORD of the Channel Specification to `00' (Transparent Mode A) together with any `Transmit Off ' channel command. This ensures octet to timeslot aligned transmission after re-initialising the channel again. - Transmit Abort (not supported by LBI) TI =`0', TO = `1', TA = `1' (clears transmit off condition, sets transmit abort condition, affects only the serial interface) This abort is performed in the transmit formatter at the serial interface. The currently transmitted frame is aborted by the sequence: 011 1111 1111 1111 for HDLC for TMB 00H for TMR 0000H 3 frames with erroneous synchronization pattern for V.110/X.30 TFLAG for TMA, FA = `1' FF for TMA, FA = `0'. - Afterwards or, if no frame is currently sent, directly inter frame time fill: 7E for HDLC and IFTF = `0' FF for HDLC and IFTF = `1' 00 for TMB, TMR, V.110/X.30 TFLAG for TMA, FA = `1' FF for TMA, FA = `0'
Data Sheet 297 2001-02-14
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Host Memory Organization is sent. During transmit abort the TF does not access the Tx buffer. The handling of the link list is not affected by the transmit abort, i.e. the device keeps the TB full. When the transmit abort is withdrawn, the Tx formatter continues the transmission with the data stored in TB. In the case of HDLC or TMB or TMR mode the remaining data of the aborted HDLC or TMB frame is sent as a new independent frame. To avoid this problem the link list must be reinitialized by a transmit initialization command together with the revoking of the transmission abort. Another proper use of the transmit abort command consists in setting the last descriptor of the last frame to be transmitted with HOLD = `1' and waiting for the device to poll the HOLD bit (ITBS + 2) times where ITBS is the number of DWORDs assigned to this channel currently. Afterwards TB is empty and the transmit abort then issued does not abort a currently sent frame. The same procedure can also be used for the transmit off command. - Transmit Jump TI = `1', TO = `0', TA = `0' (clears a transmit off and transmit abort condition, affects only the DMA interface) This bit is set only during normal operation. Then the MUNICH32X branches to the transmit descriptor (FTDA) specified in the CCB after finishing the current Tx descriptor without interrupting or aborting the transmitted frame. The DMA controller will proceed finishing the current transmit descriptor as usual and afterwards branch to the new descriptor specified by FTDA. If the current descriptor does not include a frame end (FE = 0) (HDLC, TMB, TMR) the DMA controller will link the following data section(s) of the `new' descriptor chain to the opened frame. This may generate unexpected frames. - Transmit Initialization TI = `1', TO = `0', TA = `1' (clears a previous transmit abort condition, affects the DMA interface and the serial interface) Before the MUNICH32X has received a transmit initialization command, it will not transmit correctly on the channel. This command should therefore be the first channel command after a pulse at the reset pin for a channel. FTDA is then the address of the starting point of the Tx descriptor for chaining list. In this case the transmit initialize command should be accompanied by the NITBS bit set and a reasonable value for ITBS (0 < ITBS < 64). If the command is issued during normal operation it only affects the DMA. The MUNICH32X stops processing of the current link list and branches to the Tx descriptor at the FTDA address. The data stored in the TB are discarded and the TB is filled with the data of the new descriptor.
Data Sheet
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2001-02-14
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Host Memory Organization 3. Second Transmit Command Group - Transmit Hold (not supported by LBI) TH; setting this bit causes the device to finish transmission of the current frame (HDLC, TMB, TMR mode) the current data (TMA mode) or leads to an abort with 3 frames with `0' bits (V.110/X.30 mode). Afterwards for HDLC mode and IFTF = `1' FFH fill characters HDLC mode and IFTF = `0' 7EH fill characters V.110/X.30-mode 00H fill characters TMA mode and FA =`1' TFLAG fill characters, if no poll access was done; else: FFH fill characters TMA mode and FA = `0' FFH fill characters TMB/TMR 00H fill characters are sent until TH is withdrawn by a further action specification affecting the channel specification of this channel. Afterwards no further access to the TB from TF is done, therefore no further data are fetched from host memory and the polling of the HOLD bit in the Tx descriptor stops. In order to send the required frames/data before TH is active, the corresponding procedure as described for the transmit abort command should be used. * General Notes on Transmit Commands: 1. After reset, a channel having a time slot with TTI = `0' should issue transmit off commands and TH = `1' until it is required to be used. 2. When it is supposed to be used it should be issued a transmit initialization command and TH = `0' before using any other Tx channel commands (together with NITBS = `1', ITBS `0'). 3. To shut down a channel in transmit direction one should first set it into the transmit abort condition or use the TH bit with the proper procedure. One should leave it in that condition for 32, 240, 32, 32, 8 bits for HDLC, V.110/X.30,TMB, TMR, TMA respectively and then set it into the transmit off condition. 4. Before changing the MODE, CRC, CS, TRV, INV, TFLAG bits or TTI or time slot assignment or the fill/mask bits or the ITBS the channel should be shut down. The bits should be changed while issuing the transmit off command. 5. To revive a channel after it has been shut down one should use the transmit initialization command. 6. For V.110/X.30-mode the first descriptor after reviving from shut down or initialization after reset must have the V.110-bit set and contain the E-, S-, X-bits. 7. To switch to a new starting point of a Tx descriptor chain one should preferably use the transmit jump command, only exceptionally the fast transmit abort command and never the transmit initialize command.
Data Sheet
299
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Host Memory Organization 8. To issue channel commands not affecting the transmit side one should issue - TH with the last set value - a transmit clear command if neither a transmit off nor a transmit abort condition is set - a transmit off if a transmit off condition is set - a transmit abort if a transmit abort condition is set. 9. Bit combinations in the first Tx command group not described are reserved. 10. Set NITBS = `1' preferably in conjunction with a transmit initialize and transmit clear command if TB is to be newly configured, otherwise program NITBS = `0'. 11. For new configuration of a channel (`de-allocation of ITBS') consider two cases: a) if the channel has not been initialized yet: program NITBS = `0', ITBS = `0', b) after successful initialization: program NITBS = `1', ITBS = `0', both in conjunction with transmitt off TFLAG: Transparent mode Flag; these bits are only used in the transparent mode A and constitute the fill code for flag stuffing and for flag filtering. These bits must be set to `0' if subchanneling is used in transparent mode A. Bit No. 15 is the first bit of the flag to be received/transmitted. CRC Select; only used in HDLC mode. Setting this bit to `1' causes the MUNICH32X to transfer the CRC bits to the data section in the shared memory. In receive direction the CRC check is carried out whereas in transmit direction the CRC generation is suppressed, see Chapter 4: Detailed Protocol Description for more details. Inversion; If this bit is set, all data of the channel transmitted or received by the MUNICH32X is inverted. Cyclic Redundancy Check; in HDLC mode this bit determines the CRC generator polynomial: When the CRC bit is set to `1', the 32-bit CRC is performed, otherwise the 16-bit CRC. For TMB/TMR mode this bit distinguishes: TMB: CRC = `0' TMR: CRC = `1' Note: For all other modes this bit has to be set to `0'. TRV: Transmission Rate of V.110/X.30. These signals determine the number of repeated D-bits in a V.110/X.30 frame.
CS:
INV: CRC:
Data Sheet
300
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Host Memory Organization Table 31 TRV 00 01 10 11
No. of Repetitions 7 3 1 0
Transmission Rate 600 bit/s 1200 bit/s 2400 bit/s 4.8, 9.6, 19.2, 38.4 Kbit/s
Note: In the other modes these bit fields must be programmed to `00'. FA: Flag Adjustment selected (in HDLC mode) or flag filtering (selected in transparent mode A only if all fill/mask bits of the corresponding slots are `1'). In all other modes this bit must be set to `0'. If flag adjustment is selected in HDLC mode the number of interframe time-fill characters is FNUM minus one eighth of the number of zero insertions in the frame proceeding the interframe time-fill and belonging to the same transmit descriptor as FNUM. If flag filtering is selected and fills a physical time slot in transparent mode A the flag specified in TFLAG is recognized and extracted from the data stream. In transmit direction the flag TFLAG is sent in all exception conditions, i.e. abort, idle state etc.; if flag filtering is not selected, `1'-bits are sent in this case. Flag filtering is only allowed if all fill/mask codes are set to `1', i.e. subchanneling is not allowed. If flag filtering is not selected the bits in TFLAG have to be programmed to `0' for TMA. Defines the transmission mode: 00: Transparent mode A 01: Transparent mode B or transparent mode R. 10: V.110/X.30 mode 11: HDLC mode Interframe Time-Fill; this bit determines the interframe HDLC mode: IFTF = `0': 7EH characters are sent as interframe time-fill IFTF = `1': FFH characters are sent as interframe time-fill. time-fill for
MODE:
IFTF:
FRDA:
First Rx Descriptor Address; points to the beginning of the Rx data chaining list. This descriptor is only interpreted with a fast receive abort or a receive jump or a receive initialization command. It is read but ignored with any other receive channel command. First Tx Descriptor Address; points to the beginning of the Tx data chaining list. This descriptor is only interpreted with a fast transmit abort or a transmit jump or a transmit initialization command. It is read but ignored with any other transmit channel command.
301 2001-02-14
FTDA:
Data Sheet
PEB 20321 PEF 20321
Host Memory Organization ITBS: Individual Tx Buffer Size; for undisturbed transmission the on-chip Tx buffer with a total size of 64 DWORDs stores the data before formatting and transmitting. The individual buffer size specifies the part of the on chip transmit buffer allocated to the channel. This allows a variable data buffer size if NITBS = `0', ITBS has to be programmed to `0' also; it is then read but ignored. (see Chapter 3: Basic Functional Principles).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFE IFC CH TE RE FIR FIT NITBS RI TI TO TA TH RO RA
CS INV CRC
FRDA (First Receive Descriptor Address) FTDA (First Transmit Descriptor Address) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITBS (buffer size) New ITBS Value Rcv./Xmt. Commands Transparent Mode Flags Interframe Rcv. Commands Timefill New Xmt. buffer size Fill code for flags in 0 7E (flags) (ITBS valid) (RI, RO, RA): transp. mode A (TMA only) 000 Rcv. Clear 1 FF (ones) 001 Fast Rcv. Abort (HDLC mode) Interrupt Mask CRC Select 010 Rcv. OFF SFR: Short Frame (R) CRC Generated/Stripped 0 011 Rcv. Abort Mode CRC to/from Data Section 1 IFC: Idle/Flag Change (R) 100 Rcv. Jump (HDLC mode only) CH: V.110 Frg. Chg. (R) 0 0 TMA 101 Rcv. Init. TE: ERR Interrupt (T) 0 1 TMB/TMR 110 Not Allowed RE: ERR Interrupt (R) 1 0 V.110/X30 Inversion 111 Not Allowed FIR: FI Interrupt (R) 1 1 HDLC Mode All Rcv. and Xmt. data Bits FIT: FI Interrupt (T) First Xmt. Commands in this channel are inverted. (R) Receiver Interrupt Flag Adjustment/Filtering (T) Transmitter Interrupt (TI, TO, TA): FNUM interframe timefill CRC Polynom 000 Xmt. Clear characters in HDLC mode, 001 Fast Xmt. Abort 16 Bit CRC (HDLC mode) 0 or TFLAG filtering in TMA 010 Xmt. OFF 32 Bit CRC (HDLC mode) 1 011 Xmt. Abort TMB 0 100 Xmt. Jump TMR 1 Transmission Rate of V.110/X30 101 Xmt. Init. 0 0 600 bit/s, 7 Repetitions 110 Not Allowed 0 1 1200 bit/s, 3 Repetitions 111 Not Allowed 1 0 2400 bit/s, 1 Repetitions 1 1 4.8, 9.6, 19.2, 38.4 kbit/s, 2 nd Xmt. Commands no Repetition (TH = 1) : Xmt. Hold
ITS08223
Figure 83
Channel Specification
Data Sheet
302
FA
0
TFLAG
TRV
Mode
IFTF
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Host Memory Organization
12.7
31
Current Receive and Transmit Descriptor Addresses
16 15 Current Rx Descriptor Address Channel 0 . . . Current Rx Descriptor Address Channel 31 Current Tx Descriptor Address Channel 0 . . . Current Tx Descriptor Address Channel 31 0
For easier monitoring of the link lists the addresses of the just processed descriptors are written into the CCB. The MUNICH32X changes the current descriptor address at the same time when it branches to the next descriptor.
Data Sheet
303
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Host Memory Organization
12.8
31 0 30
Receive Descriptor
29 HI 28 27 26 25 24 23 22 NO Next Rx Descriptor Pointer Rx Data Pointer 21 20 19 18 17 16
HOLD
FE 15
C 14 13
0 12 11 10 9 8 7
BNO 6 5 4 3 2 1 0
0000H Next Rx Descriptor Pointer Rx Data Pointer Status 00H
The Rx Descriptor consists of 4 DWORDs. During run-time, the MUNICH32X reads the Rx Data Pointer. After the MUNICH32X accesses an Rx descriptor, it updates the appropriate current Rx descriptor address in the CC Block.
Data Sheet
304
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Host Memory Organization The Rx Descriptor is accessed in the following order (assuming a normal complete access with HOLD = `0', i.e. no polling): 1. Access n: 2. Access n + 1: 3. Access n + 2: 4. Access n + 3: 5. Access n + 4: 6. Access n + 5: 7. Access n + 5: Read the first descriptor DWORD Read the next Rx descriptor pointer Read the Rx data pointer Write the current Rx descriptor address to Control and Configuration Block (CCB) Data Transfer Write the fourth descriptor DWORD (number of received data bytes, status information) Handle selected interrupts
Note: The MUNICH32X does not update the fourth DWORD if the receive initialization command is used during normal operation (see Chapter 12.5) The descriptor bit fields have the following meaning: HOLD: Setting the HOLD bit by the host prevents the device from branching to the next descriptor. The current data section is still filled. - Afterwards the fourth descriptor DWORD is written by the MUNICH32X. For HDLC, TMB, TMR the FE and C bits are set. If the frame could not completely be stored into the data section the RA bit is set in the status. An interrupt with set FI bit is generated, and in case the frame was aborted, the ERR bit is also set. For TMA, V.110/X.30 the C bit and the RA bit are set and an interrupt with set ERR but with FI = `0' is generated. - Afterwards the device starts polling the HOLD bit. Received data and received events normally leading to interrupts (with RT = 1) are discarded until HOLD = `0' is detected. Each 1 ... 4 byte data word or interrupt event normally leading to an access now results in a poll cycle. Whenever HOLD = `1' is detected the next Rx descriptor address is read but ignored. - When HOLD = `0' is detected * for HDLC, TMB, TMR the device continues to discard data until the end of a received frame or an event leading to an interrupt (with RT = `1') is detected. Afterwards the next received frame is transferred into the next Rx descriptor. Interrupts are also generated again. * For V.110/X.30, TMA the device puts the next data into the next Rx descriptor. Interrupts are also generated again. The HOLD condition is also discarded upon detection of a receive jump, fast receive abort or receive initialization command. The MUNICH32X then branches to the Rx descriptor determined by FRDA even though the HOLD bit in the current Rx descriptor may still be `1'.
Data Sheet
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Host Memory Organization For a description of the complete polling process of the MUNICH32X refer to the descriptions of MODE2 and TXPOLL registers. HI: NO: Host initiated interrupt; if the HI bit is set, MUNICH32X generates an interrupt with set HI bit after receiving all data bytes. This defines the byte size of the receive data section allocated by the host. Because MUNICH32X always writes DWORDs the number of bytes (data section size) must be a multiple of 4 and greater or equal to 4. The maximum data section size is 8188 bytes. After reception of an HDLC frame with a data byte number not divisible by 4 the MUNICH32X first transfers the greatest entire (number of data bytes/4) in DWORDs. Then the remainder of the data bytes is transferred in another DWORD, where the non-significant bytes are filled with random values. They should not be interpreted. For example a HDLC frame with one data byte is received: Rx Descriptor 00000000.00001000.00000000.00000 Next Rx Descriptor Pointer Rx Data Pointer 11000000.00000001.Status.00000000 The data bytes are stored in the Rx data section in little endian format . FE: Frame End: The frame end bit is set to `1' only in HDLC, TMB, TMR mode and indicates that a receive frame has ended in this Rx descriptor. For TMA and V.110/X.30 the bit is always `0'. FE = `0' in HDLC, TMB, TMR mode means that frame continues in the next Rx descriptor or that it filled the current receive data section exactly (BNO = NO). In this case, the next Rx descriptor will have FE = `1', C = `1', BNO = `0', and no data bytes are stored in the corresponding data section. Note: For LBI FE is set to `1' in general, since only HDLC is supported. Rx Data Section XX.XX.XX.data
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Host Memory Organization C: This bit field is set by MUNICH32X if * it completes filling the data section (BNO = NO) FE = `0', Status = 00H * it was aborted by a fast receive abort channel command Status = 02H * for HDLC, TMB, TMR if the end of a frame was stored in the receive data section FE = `1', status gives the receive status determined by Rx descriptor (interrupt with set FI bit is generated) * for V.110/X.30 mode if the 3 contiguous frames with errors in the synchronization pattern are received FE = `0', status = 20H or status = 21H (interrupt with set ERR bit) * for V.110/X.30 mode if the data could not be transferred to the shared memory due to Rx buffer inaccessibility FE = `0', Status = 01H or Status = 21H (interrupt with set ERR bit). C indicates that the fourth DWORD of the Rx descriptor was written by the MUNICH32X. Afterwards the MUNICH32X writes the next Rx descriptor address into CCB. Then it branches to this descriptor immediately. MUNICH32X writes the number of data bytes it has stored in the current data section into BNO. The MUNICH32X writes the status information into the Status byte whenever it sets the C bit field. If the status information does not equal 00H or 40H, an interrupt with ERR bit set is generated. The status then supports locating or analyzing the receive error. The following table gives a general overview over the different status bits in relation to the channel modes.
BNO: Status:
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Host Memory Organization Status Information PCM Core: 7 0 HDLC (CS = 0) HDLC (CS = 0) V.110/X.30 TMB TMR TMA LBI: 7 0 HDLC 0 0 0 0 0 0 0 0 0 0 0 RA I 0 0 0 0 0 0 0 0 0 SF NI 0 0 0 0 0 LOSS 0 0 I 0 0 0 CRCO ILN ILN 0 0 0 0 NOB IL IL 0 IL IL 0 LFD I I 0 I I 0 RA I I IF IF IF IF 0 ROF I I I I I 0
Where `0' means that in the corresponding mode the bit is always `0'. NI ILN IL I IF I, IF, IL, ILN means the bit may be `1' or `0' but does not cause an interrupt with ERR bit set. means that it may be `1' or `0' but should not be evaluated if LFD or NOB is also `1'. means that it may be `1' or `0' but should not be evaluated if LFD = `1'. means that it may `1' or `0'. means that it may be `1' only after a fast receive abort channel command or detection of a HOLD bit in the current receive descriptor. lead to an interrupt with ERR bit set.
Note: For HDLC, TMB, TMR the status word is only valid if the FE bit is set.
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Host Memory Organization The meaning of the individual status bits is as follows: SF = `1' (HDLC mode with CS = `0' only): The device has received a frame which includes: 32 bits between start flag and end flag or end abort flag for CRC16 48 bits between start flag and end flag or end abort flag for CRC32, i.e. BNO was 1 or 2. Three contiguous frames with errors in the synchronization pattern were detected. A frame with a CRC error was detected. CRCO = `0' means the frame had no CRC error. A frame whose bit contents were not divisible by 8 was detected. NOB = `0' means that the frame contents were divisible by 8. Long frame detected. If this bit is set a frame whose bit contents were > MFL was detected and aborted. The reception will be continued as soon as a flag is recognized. Receive Abort; this bit indicates that for HDLC: the frame was ended by an abort flag (7FH) or by a receive abort command or a fast receive channel command or by a HOLD bit set in the current Rx descriptor. for V.110/X.30, TMB, TMR, TMA: the frame or data were aborted by a fast receive abort channel command or a HOLD bit set in the current Rx descriptor. An overflow of the internal receive buffer RB has occurred and lead to a loss of data.
LOSS = `1' CRCO = `1' NOB = `1' LFD = `1'
RA = `1'
ROF = `1'
Note: If ROF without FO interrupt is generated for a channel * for HDLC, TMB, TMR only the last part of one frame has been lost. * For V.110/X.30 only data but no status information (change E-, S-, X-bits, Loss) has been lost. Note: In case of multiple errors all relevant bits are set. In case of ROF = `1' only the error conditions of the frame within which the overflow occurred are reported. Later frames that are aborted do not change the status. Rx Data Pointer: This 32-bit pointer contains the start address of the receive data section.
Data Sheet
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Host Memory Organization Rx Descriptor Pointer: This 32-bit pointer contains the start of the next Rx descriptor. It is not used if a receive jump, fast receive abort or receive initialize command is detected while the MUNICH32X still writes data into the current receive descriptor or polls the HOLD bit. In this case FRDA is used as a pointer for the next Rx descriptor to be branched to.
Data Sheet
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Host Memory Organization
12.9
31 30
Transmit Descriptor
29 28 27 26 25 24 23 22 NO Next Tx Descriptor Pointer Tx Data Pointer 21 20 19 18 17 16
FE HOLD HI
15 V.110
14 0
13 0
12
11
10
9
8
7
6
5 FNUM
4
3
2
1
0
NO13 CSM Tx Data Pointer
Next Tx Descriptor Pointer
A Transmit Descriptor consists of 3 DWORDs. During run-time, the MUNICH32X reads the Transmit Data Pointer. After accessing an Tx descriptor, it updates the appropriate current Tx descriptor address in the CC Block. The Tx Descriptor is accessed in the following order (assuming a normal complete transfer with HOLD = `0', i.e. no polling): 1. Access n: 2. Access n + 1: 3. Access n + 2: 4. Access n + 3: 5. Access n + 4: 6. Access n + 5: Read the first descriptor DWORD Read the next Tx descriptor pointer Read the Tx data pointer Write the current Tx descriptor address to Control and Configuration Block (CCB) Data Transfer Handle selected interrupts
The descriptor bit fields have the following meaning:
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Host Memory Organization FE: Frame End; this bit is valid in all modes. It indicates that after sending the data in the transmit data section - the device generates an interrupt with FI bit set for HDLC, TMB, TMR, TMA ERR bit set for V.110/X.30 - the device then sends (not supported by LBI) for HDLC, IFTF = `0' * (FNUM + 1) x 7EH for HDLC, IFTF = `1', FNUM 1 * 7EH, (FNUM - 1) x FFH, 7EH for HDLC, IFTF = `1', FNUM = 0 * 7EH * (FNUM + 1) x 00H for TMB, TMR (FNUM 1) for TMR, FNUM = 0 * 000H * (FNUM + 1) x TFLAG for TMA, FA = `1' * (FNUM +1) x FFH for TMA, FA = `0' * 3 frames with synchronization errors for V.110/X.30 before starting with the data of the next Tx descriptor. If the data of the next Tx descriptor are not available in time (e.g., because the descriptor has FE and HOLD set) the device sends the interframe time-fill indefinitely. HOLD: If the MUNICH32X detects a HOLD bit it - generates an interrupt with bit ERR set in the case of frame end bit FE = `0' and/or V.110/X.30 mode was selected in the transmit descriptor; in HDLC mode the corresponding data section is sent and terminated by an abort sequence; In the case of FE = `1' and not V.110/X.30 mode selected: - the device then sends at least (not supported by LBI) * (FNUM + 1) x 7FH for HDLC, IFTF = `0' * 7EH, FNUM x FFH for HDLC, IFTF = `1' * (FNUM + 1) x 00H or TMB, TMR (FNUM 1) * 0000H for TMR, FNUM = 0 * (FNUM + 1) x TFLAG for TMA, FA = `1' * (FNUM + 1) x FFH for TMA, FA = `0' * (in TMA mode, after TFLAGs, `1's are sent until next sync. pulse) * three frames with synchronization errors for V.110/X.30. - It polls the HOLD bit and the next transmit descriptor address, but does not branch to a new descriptor until the HOLD bit is reset. The next transmit descriptor address is read but not interpreted as long as HOLD = `1'. Therefore it can be changed together with setting HOLD = `0'. The poll mechanism depends on the settings in registers MODE2 and TXPOLL (automatic polling not supported by LBI). - The device sends interframe time-fill until HOLD = `0' is polled. The HOLD condition is also discarded if a transmit jump, fast transmit abort or transmit initialization command is detected during the polling. The
Data Sheet
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Host Memory Organization MUNICH32X then branches to the Tx descriptor determined by FTDA even though the HOLD bit of the current Tx descriptor may still be `1'. HI: NO: Host initiated Interrupt; if the HI bit is set, the MUNICH32X generates an interrupt with set HI bit after transferring all data bytes. This byte number (together with NO13) defines the number of bytes stored in the data section to be transmitted. A Tx descriptor and the corresponding data section must contain at least either one data byte or a frame end indication. Otherwise an interrupt with set ERR bit is generated. This bit indicates that in the corresponding data section the E-, S- and X-bits of the following V.110/X.30 frame are stored. The MUNICH32X reads these bits and inserts them into the next possible V.110/X.30 frame. The data section may contain only the two bytes specified in the next figure (in little endian format). The first Tx descriptor after a transmit initialization channel command must have the V.110 bit set if it revives the channel from a transmit off condition or after a reset. Not supported by LBI. This bit field is the MSB of NO.
V.110:
NO13:
Tx Descriptor Data Section in V.110 Mode (Not supported by LBI.) 31 E7 15 30 E6 14 29 E5 13 28 E4 12 27 E3 11 26 E2 10 25 E1 9 24 SB 8 23 SA 7 22 X 6 21 0 5 20 0 4 19 0 3 18 0 2 17 0 1 16 0 0
0000H CSM: CRC Select per Message: This bit is only valid in HDLC mode with CS = 0 and only in conjunction with the FE bit set. If set, it means that no FCS is generated automatically for the frame finished in this transmit descriptor. FNUM denotes the number of interframe time-fill characters between 2 HDLC or TMB frames. For X.30/V.110 these bits have to be programmed to `0'. FNUM = 0 means that after the current frame only 1 character (7EH for HDLC and 00H for TMB, 000H for TMR, TFLAG, TFLAG for TMA, FA = `1'; FFH for TMA, FA = `0') is sent before the following frame (shared flags). FNUM = 1 means that after the current frame 2 characters (7EH 7EH for HDLC and 00H 00H for TMB and TMR, TFLAG, TFLAG for TMA, FA = `1';
FNUM:
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Host Memory Organization FF FFH for TMA, FA = 0) are sent before the following frame (non shared flags). FNUM = 2 means that after the current frame 3 characters (7EH 7EH 7EH (IFTF = `0') or 7EH FFH 7EH (IFTF = `1') for HDLC and 00H 00H 00H for TMB and TMR, TFLAG, TFLAG, TFLAG for TMA (FA = `1'); FF FF FFH for TMA, (FA = 0)) are sent. FNUM = k means that after the current frame k + 1 characters are sent (k + 1) times 7EH for ITFT = `0' and HDLC 7EH, (k - 1) times FFH, 7EH for ITFT = `1' and HDLC for TMB, TMR (k + 1) times 00H (k + 1) times TFLAG for TMA, FA = `1' (k + 1) times FFH for TMA, FA = `0'. For HDLC mode, FNUM is reduced by one eighth of the number of zero insertions, if FA is set. If the reduction would result in a negative number of interframe time-fill characters it is programmed to `0'. Tx Data Pointer: This 32-bit pointer contains the start address of the Tx data section. Although MUNICH32X works only DWORD oriented, it is possible to begin a Tx data section at an odd address. The two least significant bits (ADD) of the Tx data pointer determine the beginning of the data section and the number of data bytes in the first DWORD of the data section, respectively. ADD: 00 = 4 bytes 01 = 3 bytes 10 = 2 bytes 11 = 1 byte MUNICH32X reads the first DWORD and discards the unused least significant bytes. The NO establishes (determines) the end of the data section, whereas the remainder of I (NO ADD)/ 4 I defines the number of bytes in the last DWORD of the data section. MUNICH32X reads the last DWORD and discards the unused most significant bytes of the last DWORD. If the first access is the same as the last access, ADD specifies the beginning of the data section and NO the number of data bytes in the DWORD. All unused bytes are discarded.
Data Sheet
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Host Memory Organization For example: 11 10 1) ADD = 01, NO = 8, byte swap bit field CONF.LBE = `0' 01 - byte 3 byte 7 2) ADD = 00, NO = 8 11 10 01 00 byte 0 byte 4 - 3) ADD = 10, NO = 1 11 - - - - - 10 byte 0 - - - 01 - - - This 32-bit pointer contains the start address of the next Tx descriptor. After sending the indicated number of data bytes, MUNICH32X branches to the next Tx descriptor to continue transmission. The Tx descriptor is read entirely at the beginning of transmission and stored in an on-chip memory. Therefore all information in the next descriptor must be valid when MUNICH32X branches to this descriptor when HOLD = `0'. For HOLD = `1' the next Tx descriptor pointer is polled together with HOLD; the next Tx descriptor must be valid, when HOLD = `0' is polled. It is not used if a transmit jump, fast transmit abort or transmit initialization channel command is detected while the MUNICH32X still reads data from the current Tx descriptor or polls the HOLD bit. In this case FTDA is used as a pointer for the next Tx descriptor to be branched to. 1 DWORD is read! 00 2 DWORDs are read 3 DWORDs are read 00
byte 2 byte 1 byte 0 byte 6 byte 5 byte 4 - - -
byte 3 byte 2 byte 1 byte 7 byte 6 byte 5 - - -
Next Tx Descriptor Pointer:
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Host Memory Organization
12.10
Serial PCM Core DMA Priorities
The following table shows the prioritization of queueing DMA cycles for serial PCM core accesses to the internal system bus. Priority Highest priority - Lowest priority Interrupt Receive link list including accesses to the descriptors Transmit link list including accesses to the descriptors Configuration of a channel (action requests)
Data Sheet
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Host Memory Organization
12.11
Interrupt Queues Overview
This chapter provides an overview about all MUNICH32X interrupt vectors and the different groups of interrupt queues located in the host memory. The different vector sources can be distinguished by decoding the most significant 8 bits of each vector.
12.11.1
Serial PCM Core Interrupts
The first group consists of the Serial PCM Core Interrupts. Different vectors for receive and transmit direction are written into dedicated queues.
:
Table 32
Serial PCM Core Interrupt Vectors Short Description Serial PCM Core Interrupt Vector Rx Direction Serial PCM Core Interrupt Vector Tx Direction Reference Page 280 281
Interrupt Vector Name RX_IV TX_IV
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Host Memory Organization The corresponding queues are configured via registers listed below.
:
Table 33 Queue Name
Serial PCM Core Interrupt Queues Control Registers, Register Name RIQBA Receive Interrupt Queue Base Address RIQL Receive Interrupt Queue Length Offset Address 38H 3CH
RIQ Receive Interrupt Queue
TIQ TIQBA 30H Transmit Interrupt Queue Transmit Interrupt Queue Base Address 34H TIQL Transmit Interrupt Queue Length For detailed description of interrupt vectors refer to Chapter 12.3.
12.11.2
LBI DMA Controller Interrupts
This group consists of the LBI DMA Controller Interrupts which are generated by the LBI DMA Controller (refer to Chapter 6.5). Vectors for receive and transmit direction are written to dedicated queues.
:
Table 34
LBI DMA Controller Interrupt Vectors Short Description LBI DMA Interrupt Vector Rx Direction LBI DMA Interrupt Vector Tx Direction Reference Page 172 172
Interrupt Vector Name LDMA_IV (receive) LDMA_IV (transmit)
Receive and transmit direction is distinguished by bit `R/T' in vector LDMA_IV.
Data Sheet
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Host Memory Organization The corresponding queues are configured via registers listed below.
:
Table 35 Queue Name
LBI DMA Controller Interrupt Queues Control Registers, Register Name LRIQBA LBI Receive Interrupt Queue Base Address LRIQL LBI Receive Interrupt Queue Length LTIQBA LBI Transmit Interrupt Queue Base Address LTIQL LBI Transmit Interrupt Queue Length Offset Address 58H 5CH 50H 54H
LRIQ LBI Receive Interrupt Queue LTIQ LBI Transmit Interrupt Queue
12.11.3
* * * * *
Peripheral Interrupts
This group consists of interrupt vectors generated by the following peripheral blocks: LBI Mailbox (MB) Synchronous Serial Control Interface (SSC) IOM(R)-2 Interface General Purpose Bus LBI Pass Through Peripheral Queue Interrupt Vectors Short Description LBI Mailbox Interrupt Vector SSC Interrupt Vector (receive) SSC Interrupt Vector (transmit) Monitor Interrupt Vector C/I Interrupt Vector General Purpose Bus Interrupt Vector LBI Pass Through Interrupt Vector Reference Page 149 187 187 199 199 201 164
Table 36
Interrupt Vector Name MB_IV SSC_IV (receive) SSC_IV (transmit) IOMM_IV IOMCI_IV GP_IV LPT_IV
Data Sheet
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Host Memory Organization All peripheral interrupt vectors are written to one queue.
:
Peripheral Queue Queue Name PIQ Peripheral Interrupt Queue Control Registers, Register Name PIQBA Peripheral Interrupt Queue Base Address PIQL Peripheral Interrupt Queue Length Offset Address 14H 18H
The different vector sources can be distinguished by decoding the most significant 8 bits as shown in Figure 84.
31 MB_IV SSC_IV (receive) SSC_IV (transmit) IOMM_IV
24 23 0x00h
16 15
87 IV(15:1)
0 1
10110000
1 0 1 0 0 0 0 1 D/E 0 0 0 0 ER RX TX
IV(15:0)
1 0 1 0 0 0 0 0 D/E 0 0 0 0 ER RX TX
IV(15:0)
1 0 0 1 0 0 0 DIR Value(2:0) 1 0 CNO(2:0)
Received Byte 1
Received Byte 0
IOMCI_IV
1 0 0 1 0 0 0 1 0 0 0 0 1 CNO(2:0) 0 0 0 0 0 0 0 0 0 0 0 0
CIC(3:0)
GP_IV
10000101
0x00h
GPH(7:0)
GPL(7:0)
LPT_IV
1 0 0 0 LPTID(3:0)
GIS(7:0)
IS(7:0)
LSTAT(7:0)
ITD10846
Figure 84
Decoding of Peripheral Queue Interrupt Vectors
Data Sheet
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Host Memory Organization
Data Sheet
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Boundary Scan Unit
13
Boundary Scan Unit
In MUNICH32X a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary scan, meet the requirements given by the JTAG standard: IEEE 1149.1. Figure 85 gives an overview.
Test Access Port JTEST0 (TCK) CLOCK Clock Generation CLOCK JTEST1 (TMS) Test Control JTEST2 (TDI) Data IN JTEST3 (TDO) -Finite State Machine -Instruction Register (3 bits) -Test Signal Generator BS Data IN TAP Controller Control Bus 6 ID Data OUT SS Data OUT Data OUT n Power ON Reset Pins 1 2
Enable
Boundary Scan (n Bits)
ITB03509
Reset
Figure 85
Block Diagram of Test Access Port and Boundary Scan
Test handling is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output). Test data at TDI are loaded with a 4-MHz clock signal connected to TCK. `1' or `0' on TMS causes a transition from one controller state to an other; constant `1' on TMS leads to normal operation of the chip. If no boundary scan testing is planned TMS and TDI do not need to be connected since pull-up transistors ensure high input levels in this case. Nevertheless it would be a good practice to put the unused inputs to defined levels. In this case, if the JTAG is not used: TMS = TCK = `1'. After switching on the device (VDD = 0 to 5 V) a power-on reset is generated which forces the TAP controller into test logic reset state. TDO
Data Sheet
322
Identification Scan (32 Bits)
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Boundary Scan Unit Table 37 TDI Seq. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 RST CLK GNT REQ AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3 IDSEL AD23 AD22 AD21 AD20 AD19 AD18 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Number of Boundary Scan Cells 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Constant Value In, Out, Enable 001 100 000 000 001 111 000 000 100 000 110 000 000 000 000 000 0 0 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 Boundary Scan Sequence in MUNICH32X
Data Sheet
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Boundary Scan Unit Table 37 Boundary Scan Sequence in MUNICH32X (cont'd) TDI Seq. No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Pin AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP RESERVED1 PERR SERR PAR C/BE1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 INTA LA15 LA14 LA13 LA12 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Number of Boundary Scan Cells 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Constant Value In, Out, Enable 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
Data Sheet
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Boundary Scan Unit Table 37 Boundary Scan Sequence in MUNICH32X (cont'd) TDI Seq. No. 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Pin LA11 LA10 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 RESERVED2 W/R LBREQ LHOLD LHLDA LRDY LRD LWR LBHE LINTI2 LINTI1 LINTO LALE LCSO LCSI DACKRB DACKRA DACKTB DACKTA DRQRB DRQTB DRQRA DRQTA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I I I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O Number of Boundary Scan Cells 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 3 3 3 3 3 1 1 3 3 3 1 3 3 3 3 3 3 3 3 Constant Value In, Out, Enable 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 0 000 000 000 000 000 0 0 000 000 000 0 000 000 000 000 000 000 000 000
Data Sheet
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Boundary Scan Unit Table 37 Boundary Scan Sequence in MUNICH32X (cont'd) TDI Seq. No. 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 Pin DEMUX TEST MCS3 MCS2 MCS1 MCS0 N.C.3 MRST MTSR MCLK TXCLK TSP TXD TXDEN DRDY RXD RSP RXCLK I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I I I I Number of Boundary Scan Cells 1 1 3 3 3 3 3 3 3 3 1 1 3 3 1 1 1 1 Constant Value In, Out, Enable 0 0 000 000 000 000 000 000 000 000 0 0 000 000 0 0 0 0
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note that some output and input pins of the MUNICH32X are tested as I/O pins in boundary scan, hence using three cells. The boundary scan unit of the MUNICH32X contains a total of n = 344 scan cells. The right column of Table 37 gives the initialization values of the cells. The desired test mode is selected by serially loading a 3-bit instruction code into the instruction register via TDI (LSB first); see Table 38. EXTEST is used to examine the interconnection of the devices on the board. In this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values (`0' or `1', according to Table 37). Then the contents of the boundary scan is shifted to TDO. At the same time the next scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on.
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Boundary Scan Unit Table 38 000 001 010 011 111 others Boundary Scan Test Modes Test Mode EXTEST (external testing) INTEST (internal testing) SAMPLE/PRELOAD (snap-shot testing) IDCODE (reading ID code) BYPASS (bypass operation) handled like BYPASS
Instruction (Bit 2 ... 0)
INTEST supports internal testing of the chip, i.e. the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values (`0' or `1', according to Table 37). The resulting boundary scan vector is shifted to TDO. The next test vector is serially loaded via TDI. Then all input pins are updated for the following test cycle. Note: In capture IR-state the code `001' is automatically loaded into the instruction register, i.e. if INTEST is wanted the shift IR-state does not need to be passed. SAMPLE/PRELOAD is a test mode which provides a snap-shot of pin levels during normal operation. IDCODE: A 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to `1'. TDI 0011 0000 0000 0011 1100 0000 1000 001 1 TDO
Note: Since in test logic reset state the code `011' is automatically loaded into the instruction register, the ID code can easily be read out in shift DR state which is reached by TMS = 0, 1, 0, 0. BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.
Data Sheet
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Boundary Scan Unit
Data Sheet
328
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Electrical Characteristics
14
14.1
Electrical Characteristics
Important Electrical Requirements
VDD3 max = 3.6 V VDD5 max = 5.25 V
VDD3 = 3.3 V 0.3 V VDD5 = 5.0 V 0.25 V
During all MUNICH32X power-up and power-down situations the difference |VDD5 - VDD3| may not exceed 3.6 V. The absolute maximums of VDD5 and VDD3 should never be exceeded. Figure 86 shows that both VDD3 and VDD5 can take on any time sequence, not exceeding the maximum slew rate for VDD3 mentioned later and not exceeding a voltage difference of 3.6 V, for up to 50 ms at power-up and power-down. Within 50 ms of powerup the voltages must be within their respective absolute voltage limits. At power-down, within 50 ms of either voltage going outside its operational range, the voltage difference should not exceed 3.6 V and both voltages must be returned below 0.1 V.
Power Up V V 5 0.25 3.3 0.3 VDD5 Limit
~ ~
Power Down VDD5 Limit
VDD3 Limit
~ ~
VDD3 Limit
0.1 0 50
Within the grey boxes any shape of VDD3 and VDD5 signal is allowed with the requirements that the absolute limits of each signal are not exceeded, the slew rate recommendation for VDD3 is met to guarantee proper boundary scan reset and the voltage difference does not exceed 3.6 V. Outside the grey boxes the voltages provided to VDD3 and VDD5 should be inside the normal operation range. In this power-up example VDD5 is enabled after VDD3 reached its minimum operation value which is a typical implementation. For power-down VDD5 is switched off before VDD3.
~ ~
N
ms
N+50 t
ITD10843
Figure 86
Data Sheet
Power-up and Power-down Scenarios
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Electrical Characteristics Similar criteria also apply to power down in case of power failure situations:
V V 5 0.25 3.3 0.3
Power Failure: VDD5 Break Down VDD5 Limit
~ ~
V V 5 0.25 3.3 0.3
Power Failure: VDD3 Break Down VDD5 Limit
~ ~
VDD3 Limit
~ ~
VDD3 Limit
~ ~
0.1 0
0.1 N ms 50 t 0
Within the grey boxes any shape of VDD3 and VDD5 signal is allowed with the requirements that the absolute limits of each signal are not exceeded and the specified voltage differences are not exceeded. a. In case of VDD5 break-down the 3.6V difference is not exceeded anyway. The voltages must return below 0.1V within 50 milliseconds. a. In case of VDD3 break-down the maximum voltage difference must not exceed 4.5 V for a maximum of 15 milliseconds.The voltages must return below 0.1V within 50 milliseconds. This scenario is allowed for 2000 power failure cycles.
~ ~
~ ~
N
N+15
ms
t
ITD10844
Figure 87
Power-Failure Scenarios
Note: Siemens recommends that the VDD3 power supply rise from 0 to 3.3 V over a duration between 5 and 50 ms (slew rate range 66 to 660 V/s).
Data Sheet
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Electrical Characteristics The MUNICH32X contains an internal power-on reset generator, to reset the boundary scan state machine. A successful boundary scan reset is required for normal device operation. For boundary scan operations as well as for normal device operation the following operational conditions should be observed: A power-on reset to the boundary scan state machine is guaranteed to occur under these two conditions: * VDD3 rising slope < 0.4 V/ms, or * VDD3 voltage breakdown below 0.1 V or switch off > 20 ns combined with a VDD3 voltage breakdown below 0.1 V. A power-on reset to the boundary scan state machine will not occur under these two conditions: * VDD3 falls below 0.1 V for less than 5 ns, or * VDD3 falls to no less than 2.6 V for any length of time. The operation of the device and the boundary scan circuitry is unpredictable for any of the following conditions: * VDD3 slope > 0.5 V/ms,or * VDD3 falls below 0.1 V for a duration between 5 ns and 20 ns, or * VDD3 falls to a voltage between 0 V and 2.6 V for any duration Note: Siemens recommends that the VDD3 power supply rise from 0 to 3.3 V over a duration between 5 and 50 ms (slew rate range 66 to 660 V/second). Additional recommendations: If the pin DRDY is not used, it should be connected to VDD3 via a pull-up resistor. The pin TEST has to be tied to VSS (refer to pin description table).
Data Sheet
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Electrical Characteristics
14.2
Table 39 Parameter
Absolute Maximum Ratings
Symbol min. Limit Values max. 70 125 125 C C C 0 - - 65 - 0.4 Unit
Ambient temperature under bias Junction temperature under bias Storage temperature Voltage at any pin with respect to ground
TA TJ Tstg VS
VDD5 + 0.4 V
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
14.3
Table 40 Parameter
Thermal Package Characteristics
Symbol JA Value 40.3 Unit C/W
Thermal Package Resistance Junction to Ambient (without air flow)
Data Sheet
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Electrical Characteristics
14.4
Table 41 Parameter
DC Characteristics
TA = 0 to + 70 C; VDD5 = 5 V 5%, VDD3 = 3.3 V 0.3 V, VSS = 0 V
Symbol Limit Values min. max. 0.8 V V V - - - 0.4 2.0 - Unit Test Condition
a) Non-PCI Interface Pins
L-input voltage H-input voltage L-output voltage
VIL VIH VQL
VDD5 +
0.4 0.45
IQL = 7 mA (pin TXD) IQL = 2 mA (all others / non-PCI) IQH = - 400 A VDD3 = 3.3 V,
VDD5 = 5 V, inputs at VSS/VDD, no output loads
H-output voltage Power supply current VDD3 operational power down (no clocks)
VQH ICC3 ICC3 ICC5
P
2.4 - - - - -
VDD3
< 200 <2 <2 < 800 10
V mA mA mA mW A
Power supply current VDD5 Power dissipation Input leakage current Output leakage current
- - 0 V < VIN < VDD to 0 V 0 V < VOUT < VDD to 0 V
ILI ILQ
Note: 1. The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Note: 2. The electrical characteristics described in Section 14.2 also apply here! b) PCI Pins According to the PCI specification V2.1 from June 1, 1995. (Chapter 4: Electrical Specification for 5 V signalling)
Data Sheet
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Electrical Characteristics
14.5
Capacitances
a) Non-PCI Interface Pins Table 42 Parameter Input capacitance Output capacitance I/O-capacitance b) PCI Pins According to the PCI specification V2.1 from June 1, 1995 (Chapter 4: Electrical Specification for 5 V signalling)
TA = 25 C; VDD5 = 5 V 5%, VDD3 = 3.3 V 0.3 V, VSS = 0 V
Symbol Limit Values min. max. 5 10 15 pF pF pF - - - 1 5 6 Unit Test Condition
CIN COUT CIO
Data Sheet
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Electrical Characteristics
14.6
AC Characteristics
a) Non-PCI Interface Pins
TA = 0 to + 70 C; VDD5 = 5 V 5%; VDD3 = 3.3 V 0.3 V
Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and at 0.8 V for a logical "0". The AC testing input/output waveforms are shown below.
2.4 2.0 Test Points 0.8 0.45 0.8 2.0 Device Under Test C Load = 50 pF
ITS09800
Figure 88 b) PCI Pins
Input/Output Waveform for AC Tests
According to the PCI specification V2.1 from June 1, 1995 (Chapter 4: Electrical Specification for 5 V signalling)
14.6.1
PCI Bus Interface Timing
The AC testing input/output waveforms are shown in Figure 89 and Figure 90.
Clock
Vth Vtl
Vtest t val
Output Delay
Vtest t off t on
Device Under Test
C Load = 50 pF
TRI-STATE Output
Vtest
Vtest
ITS09801
Figure 89
PCI Output Timing Measurement Waveforms
Data Sheet
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Electrical Characteristics
Figure 90 Table 43 Symbol
PCI Input Timing Measurement Waveforms PCI Input and Output Measurement Conditions Value 2.4 0.4 1.5 2.0 Unit V V V V
Vth Vtl Vtest Vmax
The timings below show the basic read and write transaction between an initiator (Master) and a target (Slave) device. The MUNICH32X is able to work both as master and slave. As a master the MUNICH32X reads/writes data from/to host memory using DMA and burst. The slave mode is used by an CPU to access the MUNICH32X PCI Configuration Space, the on-chip registers and to access peripherals connected to the MUNICH32X Local Bus Interface (LBI).
14.6.1.1 PCI Read Transaction
The transaction starts with an address phase which occurs during the first cycle when FRAME is activated (clock 2 in Figure 91). During this phase the bus master (initiator) outputs a valid address on AD(31:0) and a valid bus command on C/BE(3:0). The first clock of the first data phase is clock 3. During the data phase C/BE indicate which byte lanes on AD(31:0) are involved in the current data phase. The first data phase on a read transaction requires a turn-around cycle. In Figure 91 the address is valid on clock 2 and then the master stops driving AD. The target drives the AD lines following the turnaround when DEVSEL is asserted. (TRDY cannot be driven until DEVSEL is asserted.) The earliest the target can provide valid data is clock 4. Once enabled, the AD output buffers of the target stay enabled through the end of the transaction. A data phase may consist of a data transfer and wait cycles. A data phase completes when data is transferred, which occurs when both IRDY and TRDY are asserted. When
Data Sheet 336 2001-02-14
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Electrical Characteristics either is deasserted a wait cycle is inserted. In the example below, data is successfully transferred on clocks 4, 6 and 8, and wait cycles are inserted on clocks 3, 5 and 7. The first data phase completes in the minimum time for a read transaction. The second data phase is extended on clock 5 because TRDY is deasserted. The last data phase is extended because IRDY is deasserted on clock 7. The Master knows at clock 7 that the next data phase is the last. However, the master is not ready to complete the last transfer, so IRDY is deasserted on clock 7, and FRAME stays asserted. Only when IRDY is asserted can FRAME be deasserted, which occurs on clock 8.
CLK 1 FRAME 2 3 4 5 6 7 8 9
AD
Address
Data 1
Data 2
Data 3
C/BE
Bus CMD
BE's
Data Transfer
Data Transfer
TRDY
DEVSEL Address Phase Data Phase Data Phase Bus Transaction Data Phase
ITD07575
Figure 91
PCI Read Transaction
14.6.1.2 PCI Write Transaction
The transaction starts when FRAME is activated (clock 2 in Figure 92). A write transaction is similar to a read transaction except no turnaround cycle is required
Data Sheet
337
Data Transfer
IRDY
Wait
Wait
Wait
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Electrical Characteristics following the address phase. In the example, the first and second data phases complete with zero wait cycles. The third data phase has three wait cycles inserted by the target. Both initiator and target insert a wait cycle on clock 5. In the case where the initiator inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are withdrawn. The last data phase is characterized by IRDY being asserted while the FRAME signal is deasserted. This data phase is completed when TRDY goes active (clock 8).
CLK 1 FRAME 2 3 4 5 6 7 8 9
AD
Address
Data 1
Data 2
Data 3
C/BE
Bus CMD
BE's-1
BE's-2
BE's-3
Data Transfer
Data Transfer
TRDY
DEVSEL Address Phase Data Phase Data Phase Bus Transaction
ITD07576
Data Phase
Figure 92
PCI Write Transaction
14.6.1.3 PCI Timing Characteristics
When the MUNICH32X operates as a PCI Master (initiator) and it either reads or writes a burst - as controlled by the on-chip DMA controller - it does not deactivate IRDY between consecutive data. In other words, no wait states are inserted by the MUNICH32X as a transaction initiator. The numbers of wait states, inserted by the MUNICH32X as initiator are listed in Table 44.
Data Sheet 338 2001-02-14
Data Transfer
IRDY
Wait
Wait
Wait
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Electrical Characteristics
.
Table 44 Transaction
Number of Wait States Inserted by the MUNICH32X as Initiator Number of Wait States 1st Data Cycle 2nd and Subsequent Data Cycles 0 0 0 0 0 0 0 1
Memory read burst Memory write burst Fast Back-to-back burst; 1st transaction Fast Back-to-back burst; 2nd and subsequent transactions
When the MUNICH32X operates as a PCI Slave (target), it inserts wait cycles by deactivating TRDY. The numbers of wait states, typically inserted by the MUNICH32X are listed in Table 44. Table 45 Transaction Configuration read Configuration write Register read Register write LBI read LBI write Number of Wait States Inserted by the MUNICH32X as Target Number of Wait States 2 0 3 0 3 0
The number of wait states inserted by the MUNICH32X as target is not critical for two reasons. One, because accesses to/via the MUNICH32X are usually kept to a minimum in a system. And two, because they are dependent on the type of access (e.g. for an access to a peripheral device on the LRDY signal).
Data Sheet
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Electrical Characteristics
tH
tL 2.4 V 2.0 V 1.5 V 0.8 V 0.4 V T
ITD07577
Voltage (V)
2 Vpp min
Figure 93 Table 46 Parameter
PCI Clock Specification PCI Clock Characteristics Symbol min. Limit Values typ. - - - - max. - - - 4 ns ns ns V/ns 30 11 11 1 Unit
CLK cycle time CLK high time CLK low time CLK slew rate (see note)
T tH
tL
-
Note: Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 93. Note: If fT is the frequency of the clock TCLK, fR the frequency of the clock RCLK and fCLK the frequency of the clock CLK the equations 7.996 x max (fT, fR) fCLK 33.33 MHz for CEPT, T1, E1 PCM mode and 3.998 x max (fT, fR) fCLK 33.33 MHz for 4.096 MHz PCM mode and 25 MHz fCLK 33.33 MHz for 8.192 MHz PCM mode describe the allowed range of frequencies for fCLK.
Data Sheet
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Electrical Characteristics Table 47 Parameter min. CLK to signal valid delay bussed signals CLK to signal valid delay point-to-point Float to active delay Active to float delay Input setup time to CLK bussed signals Input setup time to CLK point-to-point Input hold time from CLK - - - - 7 8 0 PCI Interface Signal Characteristics Limit Values typ. - - - - - - - max. 11 12 3 20 - - - ns ns ns ns ns ns ns Notes 1, 2 Notes 1, 2 - - Note 2 Note 2 - Unit Remarks
Note: Minimum times are measured with 0 pF equivalent load; maximum times are measured with 50 pF equivalent load. Note: REQ and GNT are point-to-point signals. All other signals are bussed.
Data Sheet
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Electrical Characteristics
14.6.2
De-multiplexed Bus Interface
CLK
FRAME
D (31 : 0)
Address dont care
Data
Address dont care
Data
A (31 : 2)
Address
Address
BE (3 : 0)
BE (3 : 0)
BE (3 : 0)
W/R
READ Access
WRITE Access
TRDY
ITT10451
Figure 94
Master Single READ Transaction Followed by a Master Single WRITE Transaction in De-multiplexed Bus Configuration
CLK
FRAME
D (31 : 0)
Address dont care
Data 1
Data 2
Data 3
Data 4
A (31 : 2)
Address
BE (3 : 0)
BE (3 : 0)
BE (3 : 0)
BE (3 : 0)
BE (3 : 0)
W/R
WRITE/READ Access
TRDY
ITT10452
Figure 95
Master Burst WRITE/READ Access in De-multiplexed Bus Configuration
Data Sheet
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Electrical Characteristics The timing provided in Table 37 and Table 38 can also be applied to the de-multiplexed bus interface.
.
Table 48 Parameter
Additional De-multiplexed Interface Signal Characteristics Limit Values min. typ. - - - - - - max. 18 15 - - - - ns ns ns ns ns ns - - - - - - - - 7 Unit Remarks
CLK to address bus signal valid delay CLK to W/R signal valid delay Address bus Input setup time to CLK
Address bus Input hold time 0 to CLK W/R signal Input setup time 7 to CLK W/R signal Input hold time to CLK 0
Note: The PCI parity signal PAR is not generated in de-multiplexed mode. It is driven active low by the MUNICH32X.
Data Sheet
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Electrical Characteristics
14.6.3
Local Bus Interface Timing
14.6.3.1 Local Bus Interface Timing in Slave Mode
1 4 LA15...LA0, LBHE 6 LALE 3 LCSI 3A 7 7A 5
LRD, LWR
ITD09803
Figure 96
LBI Slave: Address Timing in Multiplexed Mode
1 LA15...LA0, LBHE 3 LCSI 3A
2
LRD, LWR
ITD09804
Figure 97
LBI Slave: Address Timing in Non-Multiplexed Mode
Data Sheet
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Electrical Characteristics
8 LRD 10 LD15..LD0 17 LRDY (Note 1) Data 17A 11
9
Figure 98
LBI Slave: Read Cycle Timing
13 LWR 15 LD15..LD0 17 LRDY (Note 1) Data 17A 16
14
Figure 99
LBI Slave: Write Cycle Timing
Data Sheet
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Electrical Characteristics Table 49 Parameter LA, LBHE, setup time (Slave) LA, LBHE, hold time (Slave) LCSI setup time (Slave) LCSI hold time (Slave) LA, LBHE stable before ALE inactive (Slave) LA, LBHE hold after ALE inactive (Slave) LALE pulse width (Slave) Address latch setup time before command active (Slave) LALE to command inactive delay (Slave) LRD pulse width (Slave) LRD control interval (Slave) LD valid after LRD active (Slave) LD hold after LRD inactive (Slave) LWR pulse width (Slave) LWR control interval (Slave) LD stable before LWR inactive (Slave) LD hold after LWR inactive (Slave) LRD, LWR active to LRDY active LBI Slave Timings No. Symbol 1 2 3 3A 4 5 6 7 7A 8 9 10 11 13 14 15 16 17 Limit Values min. max. - - - - - - - - - - - 2 ns ns ns ns (ns) ns (ns) ns (ns) (ns) (ns) (ns) ns ns ns ns ns 5 5 0 0 1 Unit
tS-su(A) tS-h(A) tS-su(A) tS-h(A) tS-su(AALE)
TLBICLK
5 1
tS-h(AALE)
tS-w(ALE) tS-su(ALE) tS-rec(ALE) tS-w(RD) tS-rec(RD) tS-a(RD) tS-h(RD) tS-w(WR) tS-rec(WR) tS-su(WR) tS-h(WR) tS-d(RDY)
TLBICLK
0 1
TLBICLK
3
TLBICLK
1
TLBICLK
- 3
TLBICLK
- - - - -
TLBICLK
2
TLBICLK
1
TLBICLK
1
TLBICLK
5 2
TLBICLK
Data Sheet
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Electrical Characteristics Parameter LRD, LWR active to LRDY active No. Symbol 17A tS-h(RDY) Limit Values min. 3 max. Unit
TLBICLK
Note: TLBICLK is the LBI clock time period which depends on the LBI clock division factor.
Data Sheet
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Electrical Characteristics
14.6.3.2 Local Bus Interface Timing in Master Mode
LA15..LA0 24 DACKRA DACKRB 23 LCSO 34 LRD 25 LD15..LD0 19 LRDY (Note 1) Data 19A 26 27 Address 24B
Figure 100
LBI Master: Read Cycle Timing in Demultiplexed Mode
Address 24 24B
LA15..LA0
DACKTA DACKTB 23 LCSO 33 LWR 31 LD15..LD0 Data 19 LRDY (Note 1) 19A 30 27
Figure 101
Data Sheet
LBI Master: Write Cycle Timing in Demultiplexed Mode
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Electrical Characteristics
21 20 LALE 25 LA15..LA0 LD15..LD0 LBHE Address, LBHE Data 26
22
24 DACKRA DACKRB 23 LCSO 34 LRD 19 LRDY (Note 1) 27
28
19A
Figure 102
LBI Master: Read Cycle Timing in Multiplexed Mode
21 20
22
LALE 31 LA15..LA0 LD15..LD0 LBHE Address, LBHE Data 30
24 DACKTA DACKTB 23 LCSO 34 LWR 19 LRDY (Note 1)
28
27
19A
Figure 103
Data Sheet
LBI Master: Write Cycle Timing in Multiplexed Mode
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Electrical Characteristics Note 1: LRDY will be checked only when LRDY controlled bus cycles are enabled.
36C LHOLD (input) 36B LHLDA (output) 36A LBREQ (output) LCSO 35A
LRD/LWR
MUNICH32X requests the local bus
MUNICH32X releases the local bus on request of another device
ITT10453
Figure 104
LBI Arbitration Timing
Data Sheet
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Electrical Characteristics Table 50 Parameter LRDY stable to LRD, LWR inactive time LRDY hold after LRD, LRD inactive LALE pulse width (Master) LBI Master Timings No. Symbol 19 20 Limit Values min. max. 2 TLBICLK 0 1 1.5 (ns) Unit
tM-su(RDY) tM-w(ALE) tM-su(AALE)
19A tM-su(RDY)
LA, LBHE stable before ALE inactive (Master) 21 LA, LBHE hold after ALE inactive (Master) LCSO setup time (Master) LA, DACK, LBHE setup time (Master) LA, DACK, LBHE hold time (Master) LD valid before LRD inactive (Master) LD hold after LRD inactive (Master) LCSO hold time (Master) DACK hold time (Master) LD hold after LWR inactive (Master) LD stable after LWR active (Master) LWR pulse width (Master) LRD pulse width (Master) Last Master Cycle inactive to LHLDA active LHLDA inactive to First Master Cycle LHOLD inactive to LBREQ ,LHLDA inactive LHLDA inactive to LHOLD active
1)
TLBICLK TLBICLK 1 TLBICLK (ns)
1 TLBICLK 0 0 0 5 -2 5 10 n
1)
22 23
tM-h(AALE)
(ns) (ns)
tM-su(S) 24 tM-su(A) 24B tM-h(A) 25 tM-su(RD) 26 tM-h(RD) 27 tM-h(S) 28 tM-h(A) 30 tM-h(WR) 31 tM-su(WR) 33 tM-w(WR) 34 tM-w(RD) 35A tMLA(ARB)
- - - - - - -
ns ns ns (ns) ns (ns) ns ns ns ns ns ns (ns) ns
1 TLBICLK
1 TLBICLK
n-11)
2 TLBICLK 2 TLBICLK 2 TLBICLK 1 TLBICLK
36A tLAM(ARB)
36B tLHLR(ARB)
36C tLA-
LH(ARB) n depends on number of wait states: n = 2 + MCTC Wait State Cycles + additional LRDY Wait states
TLBICLK is the LBI clock time period which depends on the LBI clock division factor.
Data Sheet
351
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Electrical Characteristics
14.6.4
PCM Serial Interface Timing
37
39
RSP
43 42
RCLK
38 40 41
RDATA
44
46
TSP
50 49
TCLK
45 47 , 51 48
TDATA
ITT10447
Figure 105 Table 51 No. 37 38 39 40 41
PCM Interface Timings PCM Interface Timings Limit Values min. max. - - - - - ns ns ns ns ns
2001-02-14
Parameter Receive strobe guard time Receive strobe setup Receive strobe hold Receive data setup Receive data hold
352
Unit
10 5 5 5 5
Data Sheet
PEB 20321 PEF 20321
Electrical Characteristics Table 51 No. 42 43 44 45 46 47 48 49 50 51 PCM Interface Timings Limit Values min. Receive clock high width Receive clock low width Transmit strobe guard time Transmit strobe setup Transmit strobe hold Transmit data delay Transmit clock to high impedance Transmit clock high width Transmit clock low width Transmit tristate delay 30 30 20 5 5 - - 30 30 - max. - - - - - 25 25 - - 25 ns ns ns ns ns ns ns ns ns ns Unit
Parameter
Note: For complete internal or complete external loop t42 and t49 must be greater or equal to 3 times T.
Data Sheet
353
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Electrical Characteristics
14.6.5
System Interface Timing
RST
57
ITT10448
Figure 106 Table 52 No. 57
Reset Timing Reset Timing Limit Values min. max. - ns 10 CLK cycles Unit
Parameter RESET pulse width
Note: RST may be asynchronous to CLK when asserted or deasserted. Nevertheless deassertion must be clean, bounce-free edge as recommended by PCI Spec. Revision 2.1. Note: RST signal timing is independent of whether PCI or De-multiplexed mode is selected via pin DEMUX.
Data Sheet
354
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Electrical Characteristics
14.6.6
JTAG-Boundary Scan Timing
58 59 60
TCK
61 62
TMS
63 64
TDI
65
TDO
ITD09802
Figure 107 Table 53
JTAG-Boundary Scan Timing JTAG Boundary Scan Timing Limit Values min. max. - - - - - - - ns ns ns ns ns ns ns ns 166 80 80 30 10 30 20 60 Unit
No. Parameter 58 59 60 61 62 63 64 65 TCK period TCK high time TCK low time TMS setup time TMS hold time TDI setup time TDI hold time TDO valid delay
Data Sheet
355
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Electrical Characteristics
14.6.7
SSC Serial Interface Timing
MCLK 66 MCSI 67 MTSR 68 MRST 69
ITT10845
Figure 108
SSC Serial Interface Timing (Master)
Note: Figure 108 also applies to SSC slave operation. In this case `MTSR' and `MRST' are exchanged. Table 54 SSC Serial Interface Timing (Master) Limit Values min. 66 67 68 69 MCLK high to MCSi active delay MCLK high to MTSR delay (master) MCLK high to MRST delay (slave) MRST setup time (master) MTSR setup time (slave) MRST hold time MTSR hold time (slave) - - - max. 2 TCLK + 20 ns 2 TCLK + 20 ns 4 TCLK + 20 ns - - - - ns ns ns ns Unit
No. Parameter
1TCLK + 20 4TCLK + 20 1TCLK + 20 4TCLK + 20
Data Sheet
356
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MUNICH32X Bus Utilization
15
15.1
MUNICH32X Bus Utilization
General
The MUNICH32X operates on linked lists within the shared memory. Handshaking with the software also operating on the linked lists is performed via status information in the linked descriptors and interrupt vectors which are written into queues also located in the shared memory. In addition current descriptor addresses are written to the Channel Configuration Block (CCB) which provide information about the MUNICH32X current position in the linked descriptor lists. Evaluation of this current addresses depend on the software implementation. Configuration is handled via on-chip registers and through the Channel Configuration Block (CCB). The CCB is prepared by software in the shared memory and read by the MUNICH32X on request. After initialization and configuration no further on-chip register access is neccessary other than handling of exception conditions or configuration changes. * Transmit data flow: The Host CPU prepares transmit data in linked lists. The MUNICH32X gets the start address of this list via configuration procedure and starts processing the list by reading the first descriptor (3 DWORDs read burst) and the corresponding data section (multiple single DWORD read transfers depending on the packet size). After finishing one descriptor an interrupt vector is generated and written to the corresponding transmit interrupt queue. The MUNICH32X proceeds branching to the next descriptor and updating the current descriptor address in the CCB. For bus load calculation it is assumed that no linked list end condition occurs i.e. the CPU always attaches new descriptors to the chain and that one interrupt vector per packet is generated. * Receive data flow. The Host CPU prepares a linked list of `empty' receive descriptors and corresponding receive data buffers. The MUNICH32X gets the start address of this list via configuration procedure and starts reading the first descriptor (3 DWORDs read burst). Receive data is transferred to the receive data section by multiple single DWORD transfers depending on the packet size. After transfer of one complete packet the receive descriptor is finished when the MUNICH32X overwrites one DWORD in the descriptor with status and control information. One Interrupt vector is generated and written into the corresponding receive interrupt queue. The MUNICH32X proceeds branching to the next descriptor and updating the current descriptor address in the CCB. For bus load calculation it is assumed that no linked list end condition occurs i.e. the CPU always attaches new descriptors to the chain and that one interrupt vector per received packet is generated. Data flow is illustrated in Figure 109.
Data Sheet 357 2001-02-14
PEB 20321 PEF 20321
MUNICH32X Bus Utilization
:
System Overview:
Serial Line
MUNICH32X
PCI Bus
CPU
RAM
PCI Bridge
Host Bus
Data Flow:
Host RAM Receive Descriptor list
- Processing receive descriptors and writing receive data PCI Bus Load
Serial Line
Transmit Descriptor list
- Processing of receive data - Preparing transmit data
MUNICH32X
CPU
- Processing transmit descriptors and reading transmit data - writing Tx and Rc interrupt vectors - Writing current descriptor addresses
- Processing of receive and transmit interrupts - Evaluation of current descriptor pointers (optional) Receive Interrupt Queue CCB Current Rc Current Tx
ITD10847
Transmit Interrupt Queue
Figure 109
Data Flow
Data Sheet
358
2001-02-14
PEB 20321 PEF 20321
MUNICH32X Bus Utilization
15.2
PCI Bus Cycle Calculations
This chapter provides a calculation of PCI clock cycles needed for all transactions neccessary for receiving and transmitting a data packet (HDLC mode).
:
Table 55 A T Wir Wr Wiw D M Dr N
List of Abbreviations for PCI Bus Cycle Calculations PCI Address cycle PCI Turn arround cycle PCI Initial wait states on Read PCI Wait states on consecutive Read cycles within a burst transfer PCI Initial wait states on Write Data cycle Packet size in number of bytes (payload bytes between start flag and CRC) Serial line data rate (nominal) Number of DWORDs per data packet
15.2.1
Transmit Descriptor and Data Processing
* Transmit descriptor read cycles Td: Td = A + T + Wir + 3 x D + 2 x Wr + T * Transmit data read cycles Tdata: Tdata = N x [A + T + Wir + 1 x D + T] (N is the number of DWORDs equivalent to one transmit packet): N = (M + 3)/4 * Current transmit descriptor address update cycle Tdau: Tdau = A + Wiw + 1 x D + T
15.2.2
Transmit Interrupt Overhead
* Transmit interrupt vector write cycle Tiv: Tiv = A + Wiw + 1 x D + T
Data Sheet
359
2001-02-14
PEB 20321 PEF 20321
MUNICH32X Bus Utilization
15.2.3
Receive Descriptor and Data Processing
* Receive descriptor read cycles Rd: Rd = A + T + Wir + 3 x D + 2 x Wr + T * Receive data write cycles Rdata: Rdata = N x [A + Wiw + 1 x D + T] (N is the number of DWORDs equivalent to one receive packet.) * Receive descriptor update cycle Rdu: Rdu = A + Wiw + 1 x D + T * Current receive descriptor address update cycle Rdau: Rdau = A + Wiw + 1 x D + T
15.2.4
Receive Interrupt Overhead
* Receive interrupt vector write cycle Riv: Riv = A + Wiw + 1 x D + T
Data Sheet
360
2001-02-14
PEB 20321 PEF 20321
MUNICH32X Bus Utilization
15.3
PCI Bus Utilization Calculation
The effective serial data rate depends on the protocol mode. In HDLC mode with 16 bit CRC and shared flags (assuming back-to-back packet transmission and reception), the effective data rate Der is Der = Dr x M/(M + 3). The bus utilization U can now be calculated U = 1/fPCI x Der/32 x (Td + Tdata + Tdau + Tiv + Rd + Rdata + Rdu + Rdau + Riv).
Data Sheet
361
2001-02-14
PEB 20321 PEF 20321
MUNICH32X Bus Utilization
15.4
PCI Bus Utilization Example
The equations above are calculated for two cases: 1. Ideal system with parameter set: Wir = 0 Wiw = 0 Wr = 0 2. Typical system with parameter set: Wir = 7 Wiw = 1 Wr = 0 (These parameters are typical for an INTEL 430 FX PCI chipset as used on many PC and workstation platforms. Thus the same results are achieved by using a PCI analyzer running in a real system) For this calculation the serial line is operating in E1-Mode on all 32 channels with a total nominal bit rate of 2.048 MBit/s or in T1-Mode on all 24 channels with a total nominal bit rate of 1.536 MBit/s. The bus utilization is calculated depending on the packet size in number of bytes which is assumed to be constant in transmit and receive direction. The figures below show the bus utilization and how bus utilization is composed distinguished by data transfer (data sections) and control overhead (descriptors, interrupts, current pointers).
Bus Load E1 - Ideal System
ITD10848
8 % 6
Bus Load
5 4 3 Bus Load 2 Transfer of Overhead 1 Transfer of Data 0 4 12 20 28 36 44 52 60 68 76 84 92 100 108 Bytes 128
Packet Size
Figure 110
Ideal System, E1
Data Sheet
362
2001-02-14
PEB 20321 PEF 20321
MUNICH32X Bus Utilization
8 % 6
Bus Load E1 - Real System
ITD10849
Bus Load
5 Bus Load 4 Transfer of Overhead 3 2 Transfer of Data 1 0
4
12
20
28
36
44
52
60
68
76
84
92
100
108
Bytes
128
Packet Size
Figure 111
Typical System, E1
Bus Load T1 - Ideal System
8 % 6
ITD10850
Bus Load
5 4 3 2 PCI Bus Load 1 Transfer of overhead Transfer of Data 0 4 12 20 28 36 44 52 60 68 76 84 92 100 108 Bytes 128
Packet Size
Figure 112
Ideal System, T1
Data Sheet
363
2001-02-14
PEB 20321 PEF 20321
MUNICH32X Bus Utilization
6 % 5
Bus Load T1 - Real System
ITD10851
Bus Load
4 PCI Bus Load 3 Transfer of Overhead 2
1
Transfer of Data
0
4
12
20
28
36
44
52
60
68
76
84
92
100
108
Bytes
128
Packet Size
Figure 113
Typical System, T1
The control overhead per packet is constant which results in an increased bus load if the serial line data rate is achieved by very small packets. The overhead can be neglected for packet sizes greater than 32 bytes. On the serial line the 16 bit CRC and one shared flag per packet also appears as a constant overhead which reduces the effective data rate for small packets. The influence of bit-stuffing in HDLC protocol mode also reducing the effective data rate is neglected.
Data Sheet
364
2001-02-14
PEB 20321 PEF 20321
Package Outline
16
Package Outline
P-MQFP-160-1 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 365
Dimensions in mm
2001-02-14
GPM05247
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